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| author | whitequark <whitequark@whitequark.org> | 2021-07-20 10:30:39 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2021-07-20 10:30:39 +0000 |
| commit | 1a6ddf78921290851ca7bbe7605d9e146055dc39 (patch) | |
| tree | 6f8a256b79d6e1a5e29703644c24cd26f7673d28 /backends/cxxrtl | |
| parent | c2afcbe78d1cc582ad3d2f6809524d9aa8d9cb46 (diff) | |
| download | yosys-1a6ddf78921290851ca7bbe7605d9e146055dc39.tar.gz yosys-1a6ddf78921290851ca7bbe7605d9e146055dc39.tar.bz2 yosys-1a6ddf78921290851ca7bbe7605d9e146055dc39.zip | |
cxxrtl: treat wires with multiple defs as not inlinable.
Fixes #2883.
Diffstat (limited to 'backends/cxxrtl')
| -rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 56305258a..46759e8fa 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -326,8 +326,14 @@ struct FlowGraph { for (auto bit : sig.bits()) bit_has_state[bit] |= is_ff; // Only comb defs of an entire wire in the right order can be inlined. - if (!is_ff && sig.is_wire()) - wire_def_inlinable[sig.as_wire()] = inlinable; + if (!is_ff && sig.is_wire()) { + // Only a single def of a wire can be inlined. (Multiple defs of a wire are unsound, but we + // handle them anyway to avoid assertion failures later.) + if (!wire_def_inlinable.count(sig.as_wire())) + wire_def_inlinable[sig.as_wire()] = inlinable; + else + wire_def_inlinable[sig.as_wire()] = false; + } } void add_uses(Node *node, const RTLIL::SigSpec &sig) |