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| author | whitequark <whitequark@whitequark.org> | 2021-03-05 05:30:19 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-05 05:30:19 -0800 |
| commit | 9dd813374ea43e804cb3f86d8390bff46a8bcb8c (patch) | |
| tree | 90a17d2c11683a50bda221b0b1b22cb0fefbf32c /backends/cxxrtl | |
| parent | 06da2e0f18aa7d22b7a66303110d8ff0beab3ddc (diff) | |
| parent | 14ce8bdaa6a1120c48a934697488c463ffb15b48 (diff) | |
| download | yosys-9dd813374ea43e804cb3f86d8390bff46a8bcb8c.tar.gz yosys-9dd813374ea43e804cb3f86d8390bff46a8bcb8c.tar.bz2 yosys-9dd813374ea43e804cb3f86d8390bff46a8bcb8c.zip | |
Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addr
cxxrtl: follow aliases to outlines when emitting $memrd.ADDR
Diffstat (limited to 'backends/cxxrtl')
| -rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index cfb099d59..d7402087f 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1233,7 +1233,9 @@ struct CxxrtlWorker { RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()]; std::string valid_index_temp = fresh_temporary(); f << indent << "auto " << valid_index_temp << " = memory_index("; - dump_sigspec_rhs(cell->getPort(ID::ADDR)); + // Almost all non-elidable cells cannot appear in debug_eval(), but $memrd is an exception; asynchronous + // memory read ports can. + dump_sigspec_rhs(cell->getPort(ID::ADDR), for_debug); f << ", " << memory->start_offset << ", " << memory->size << ");\n"; if (cell->type == ID($memrd)) { bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones(); |