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| author | whitequark <whitequark@whitequark.org> | 2021-07-16 09:51:15 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2021-07-16 09:51:52 +0000 |
| commit | b28ca7f5accccae869aab1852c5b680147b3614b (patch) | |
| tree | 7313b9b01c13243a65ff6af228396a0f6ccc5f38 /backends/cxxrtl | |
| parent | 10c3214e566d8c763a68b7b18317171b707caca4 (diff) | |
| download | yosys-b28ca7f5accccae869aab1852c5b680147b3614b.tar.gz yosys-b28ca7f5accccae869aab1852c5b680147b3614b.tar.bz2 yosys-b28ca7f5accccae869aab1852c5b680147b3614b.zip | |
cxxrtl: don't expect user cell inputs to be wires.
Ports can be connected to constants, too. (Usually resets.)
Fixes #2521.
Diffstat (limited to 'backends/cxxrtl')
| -rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index eea8103a7..bf93c932a 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1295,7 +1295,7 @@ struct CxxrtlWorker { for (auto conn : cell->connections()) if (cell->input(conn.first)) { RTLIL::Module *cell_module = cell->module->design->module(cell->type); - log_assert(cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()); + log_assert(cell_module != nullptr && cell_module->wire(conn.first)); RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first); f << indent << mangle(cell) << access << mangle_wire_name(conn.first); if (!is_cxxrtl_blackbox_cell(cell) && wire_types[cell_module_wire].is_buffered()) { @@ -1305,7 +1305,7 @@ struct CxxrtlWorker { f << " = "; dump_sigspec_rhs(conn.second); f << ";\n"; - if (getenv("CXXRTL_VOID_MY_WARRANTY")) { + if (getenv("CXXRTL_VOID_MY_WARRANTY") && conn.second.is_wire()) { // Until we have proper clock tree detection, this really awful hack that opportunistically // propagates prev_* values for clocks can be used to estimate how much faster a design could // be if only one clock edge was simulated by replacing: |