| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | Add proc_rom pass. | Marcelina Kościelnicka | 2022-05-13 | 5 | -1/+283 | |
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| * | | Bump version | github-actions[bot] | 2022-05-10 | 1 | -1/+1 | |
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| * | | Merge pull request #3305 from jix/sva_value_change_logic | Jannis Harder | 2022-05-09 | 8 | -11/+121 | |
| |\ \ | | | | | | | verific: Improve logic generated for SVA value change expressions | |||||
| | * | | verific: Improve logic generated for SVA value change expressions | Jannis Harder | 2022-05-09 | 8 | -11/+121 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previously generated logic assumed an unconstrained past value in the initial state and did not handle 'x values. While the current formal verification flow uses 2-valued logic, SVA value change expressions require a past value of 'x during the initial state to behave in the expected way (i.e. to consider both an initial 0 and an initial 1 as $changed and an initial 1 as $rose and an initial 0 as $fell). This patch now generates logic that at the same time a) provides the expected behavior in a 2-valued logic setting, not depending on any dont-care optimizations, and b) properly handles 'x values in yosys simulation | |||||
| * | | | Merge pull request #3297 from jix/sva_nested_clk_else | Jannis Harder | 2022-05-09 | 4 | -5/+27 | |
| |\ \ \ | | | | | | | | | verific: Fix conditions of SVAs with explicit clocks within procedures | |||||
| | * | | | verific: Fix conditions of SVAs with explicit clocks within procedures | Jannis Harder | 2022-05-03 | 4 | -5/+27 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For SVAs that have an explicit clock and are contained in a procedure which conditionally executes the assertion, verific expresses this using a mux with one input connected to constant 1 and the other output connected to an SVA_AT. The existing code only handled the case where the first input is connected to 1. This patch also handles the other case. | |||||
| * | | | | Next dev cycle | Miodrag Milanovic | 2022-05-09 | 2 | -2/+5 | |
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| * | | | | Release version 0.17 | Miodrag Milanovic | 2022-05-09 | 2 | -3/+3 | |
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| * | | | | Update CHANGELOG | Miodrag Milanovic | 2022-05-09 | 1 | -0/+3 | |
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| * | | | | Update manual | Miodrag Milanovic | 2022-05-09 | 1 | -0/+44 | |
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| * | | | Merge pull request #3299 from YosysHQ/mmicko/sim_memory | Miodrag Milanović | 2022-05-09 | 4 | -3/+59 | |
| |\ \ \ | | | | | | | | | sim pass: support for memories | |||||
| | * | | | Handle possible non-memory indexed data | Miodrag Milanovic | 2022-05-06 | 1 | -8/+10 | |
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| | * | | | map memory location to wire value, if memory is converted to FFs | Miodrag Milanovic | 2022-05-04 | 1 | -0/+4 | |
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| | * | | | fix crash when no fst input | Miodrag Milanovic | 2022-05-04 | 1 | -1/+2 | |
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| | * | | | Start restoring memory state from VCD/FST | Miodrag Milanovic | 2022-05-04 | 3 | -3/+50 | |
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| | * | | | Add propagated clock signals into btor info file | Claire Xenia Wolf | 2022-05-04 | 1 | -0/+2 | |
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| * | | | Fix running sva tests | Miodrag Milanovic | 2022-05-09 | 1 | -4/+3 | |
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| * | | | Bump version | github-actions[bot] | 2022-05-08 | 1 | -1/+1 | |
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| * | | | opt_mem: Remove constant-value bit lanes. | Marcelina Kościelnicka | 2022-05-07 | 3 | -28/+145 | |
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| * | | | Bump version | github-actions[bot] | 2022-05-07 | 1 | -1/+1 | |
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| * | | | include latest abc changes | Miodrag Milanovic | 2022-05-06 | 1 | -1/+1 | |
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| * | | | include latest abc changes | Miodrag Milanovic | 2022-05-06 | 1 | -1/+1 | |
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| * | | | Merge pull request #3300 from imhcyx/master | Miodrag Milanović | 2022-05-06 | 1 | -1/+1 | |
| |\ \ \ | | | | | | | | | memory_share: fix wrong argidx in extra_args | |||||
| | * | | | memory_share: fix wrong argidx in extra_args | imhcyx | 2022-05-05 | 1 | -1/+1 | |
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| * | | | | Include abc change to fix FreeBSD build | Miodrag Milanovic | 2022-05-06 | 1 | -1/+1 | |
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| * | | | Bump version | github-actions[bot] | 2022-05-05 | 1 | -1/+1 | |
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| * | | | abc: Use dict/pool instead of std::map/std::set | Marcelina Kościelnicka | 2022-05-04 | 1 | -14/+14 | |
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| * | | Bump version | github-actions[bot] | 2022-05-03 | 1 | -1/+1 | |
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| * | | AIM file could have gaps in or between inputs and inits | Miodrag Milanovic | 2022-05-02 | 1 | -3/+6 | |
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| * | | Bump version | github-actions[bot] | 2022-04-30 | 1 | -1/+1 | |
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| * | | Merge pull request #3294 from YosysHQ/micko/verific_merge_past_ff | Miodrag Milanović | 2022-04-29 | 1 | -0/+1 | |
| |\ \ | | | | | | | Ignore merging past ffs that we are not properly merging | |||||
| | * | | Ignore merging past ffs that we are not properly merging | Miodrag Milanovic | 2022-04-29 | 1 | -0/+1 | |
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| * | | Bump version | github-actions[bot] | 2022-04-26 | 1 | -1/+1 | |
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| * | | Add missing parameters for ecp5 | Rick Luiken | 2022-04-25 | 2 | -1/+2 | |
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| * | | Merge pull request #3287 from jix/smt2-conditional-store | Jannis Harder | 2022-04-25 | 1 | -2/+4 | |
| |\ \ | | | | | | | smt2: Make write port array stores conditional on nonzero write mask | |||||
| | * | | smt2: Make write port array stores conditional on nonzero write mask | Jannis Harder | 2022-04-20 | 1 | -2/+4 | |
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| * | | | Merge pull request #3257 from jix/tribuf-formal | Jannis Harder | 2022-04-25 | 1 | -3/+46 | |
| |\ \ \ | | | | | | | | | tribuf: `-formal` option: convert all to logic and detect conflicts | |||||
| | * | | | tribuf: `-formal` option: convert all to logic and detect conflicts | Jannis Harder | 2022-04-12 | 1 | -3/+46 | |
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| * | | | | Merge pull request #3290 from mpasternacki/bugfix/freebsd-build | Miodrag Milanović | 2022-04-25 | 1 | -0/+3 | |
| |\ \ \ \ | | | | | | | | | | | Fix build on FreeBSD, which has no alloca.h | |||||
| | * | | | | Fix build on FreeBSD, which has no alloca.h | Maciej Pasternacki | 2022-04-24 | 1 | -0/+3 | |
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| * | | | | Merge pull request #3289 from YosysHQ/micko/sim_improve | Miodrag Milanović | 2022-04-25 | 2 | -29/+74 | |
| |\ \ \ \ | |/ / / |/| | | | Simulation improvements | |||||
| | * | | | Match $anyseq input if connected to public wire | Miodrag Milanovic | 2022-04-22 | 1 | -6/+12 | |
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| | * | | | Treat $anyseq as input from FST | Miodrag Milanovic | 2022-04-22 | 1 | -0/+21 | |
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| | * | | | Ignore change on last edge | Miodrag Milanovic | 2022-04-22 | 1 | -4/+5 | |
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| | * | | | Last sample from input does not represent change | Miodrag Milanovic | 2022-04-22 | 1 | -1/+2 | |
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| | * | | | latches are always set to zero | Miodrag Milanovic | 2022-04-22 | 1 | -6/+1 | |
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| | * | | | If not multiclock, output only on clock edges | Miodrag Milanovic | 2022-04-22 | 1 | -0/+18 | |
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| | * | | | Set init state for all wires from FST and set past | Miodrag Milanovic | 2022-04-22 | 1 | -13/+12 | |
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| | * | | | Fix multiclock for btor2 witness | Miodrag Milanovic | 2022-04-22 | 1 | -5/+9 | |
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| * | | | Bump version | github-actions[bot] | 2022-04-19 | 1 | -1/+1 | |
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