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author | Miodrag Milanovic <mmicko@gmail.com> | 2022-05-09 09:53:01 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-05-09 09:53:01 +0200 |
commit | 65f70b9d507834601b6421e5782f2a8be0a938eb (patch) | |
tree | 1f5c80dffb8e6b5696a8f0098868da37c3d387ce | |
parent | 58b23954e89a75e726d98716d5029f148c804073 (diff) | |
download | yosys-65f70b9d507834601b6421e5782f2a8be0a938eb.tar.gz yosys-65f70b9d507834601b6421e5782f2a8be0a938eb.tar.bz2 yosys-65f70b9d507834601b6421e5782f2a8be0a938eb.zip |
Update manual
-rw-r--r-- | manual/command-reference-manual.tex | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index e68da3318..bafce6de6 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -2592,6 +2592,28 @@ the resulting cells to more sophisticated PAD cells. Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode. \end{lstlisting} +\section{jny -- write design and metadata} +\label{cmd:jny} +\begin{lstlisting}[numbers=left,frame=single] + jny [options] [selection] + +Write a JSON netlist metadata for the current design + + -o <filename> + write to the specified file. + + -no-connections + Don't include connection information in the netlist output. + + -no-attributes + Don't include attributed information in the netlist output. + + -no-properties + Don't include property information in the netlist output. + +See 'help write_jny' for a description of the JSON format used. +\end{lstlisting} + \section{json -- write design in JSON format} \label{cmd:json} \begin{lstlisting}[numbers=left,frame=single] @@ -7647,6 +7669,11 @@ This pass transforms $mux cells with 'z' inputs to tristate buffers. -logic convert tri-state buffers that do not drive output ports to non-tristate logic. this option implies -merge. + + -formal + convert all tri-state buffers to non-tristate logic and + add a formal assertion that no two buffers are driving the + same net simultaneously. this option implies -merge. \end{lstlisting} \section{uniquify -- create unique copies of modules} @@ -8428,6 +8455,23 @@ a tool for Coarse-Grain Example-Driven Interconnect Synthesis. http://bygone.clairexen.net/intersynth/ \end{lstlisting} +\section{write\_jny -- generate design metadata} +\label{cmd:write_jny} +\begin{lstlisting}[numbers=left,frame=single] + jny [options] [selection] + + -no-connections + Don't include connection information in the netlist output. + + -no-attributes + Don't include attributed information in the netlist output. + + -no-properties + Don't include property information in the netlist output. + +Write a JSON metadata for the current design +\end{lstlisting} + \section{write\_json -- write design to a JSON file} \label{cmd:write_json} \begin{lstlisting}[numbers=left,frame=single] |