aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Merge branch 'master' of https://github.com/YosysHQ/yosys into ↵Benedikt Tutzer2019-10-1525-61/+345
|\ | | | | | | feature/python_wrappers/globals_and_streams
| * Merge pull request #1448 from YosysHQ/daveshah1-sv-experimentsClifford Wolf2019-10-1417-20/+315
| |\ | | | | | | Typedef support (with wrong syntax)
| | * Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-1417-20/+315
| | |\ | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | * frontends/ast: code styleDavid Shah2019-10-031-2/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * sv: Improve testsDavid Shah2019-10-038-7/+30
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * sv: Fix typedefs in blocksDavid Shah2019-10-031-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * sv: Disambiguate interface portsDavid Shah2019-10-031-3/+19
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * Update CHANGELOG and READMEDavid Shah2019-10-032-0/+3
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * sv: Add test scripts for typedefsDavid Shah2019-10-035-0/+31
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * sv: Fix memories of typedefsDavid Shah2019-10-031-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * sv: Add %expectDavid Shah2019-10-031-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * sv: Add support for memories of a typedefDavid Shah2019-10-032-6/+30
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * sv: Add support for memory typedefsDavid Shah2019-10-033-3/+44
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * sv: Fix typedefs in packagesDavid Shah2019-10-032-4/+21
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * sv: Fix typedef parametersDavid Shah2019-10-034-9/+70
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-036-11/+111
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | Merge pull request #1446 from YosysHQ/dave/ecp5-ioffDavid Shah2019-10-143-8/+16
| |\ \ \ | | |/ / | |/| | ecp5: Use IOLOGIC flipflops
| | * | ecp5: Add ECLKBRIDGECS blackboxDavid Shah2019-10-111-0/+7
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | ecp5: Add attrmvcp to copy syn_useioff to driving FFDavid Shah2019-10-101-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | ecp5: Set syn_useioff on IO FFs to enable packingDavid Shah2019-10-101-8/+8
| |/ / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | Merge pull request #1445 from YosysHQ/mwk/xilinx_ibufgMiodrag Milanović2019-10-105-33/+14
| |\ \ | | | | | | | | xilinx: Add simulation model for IBUFG.
| | * | xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-105-33/+14
| |/ /
* | | Fix renaming all classes to Cpp*Benedikt Tutzer2019-10-091-2/+2
| | | | | | | | | | | | | | | | | | (This is only relevant for classes that are exposed twice, one time as a base class and one time as a derived class that can in turn be overridden in python, but actually all others were renamed)
* | | Expose global variables and allow logging to python streamsBenedikt Tutzer2019-10-091-6/+286
|/ / | | | | | | | | | | Global variables are now accessible via the Yosys class. To capture Yosys output, once can now register an output stream in Pyosys.
* | Revert "Add test that is expecting to fail"Eddie Hung2019-10-081-20/+0
| | | | | | | | This reverts commit c28d4b804720c2cf0086e921748219150e9631b5.
* | Revert "Be mindful that sigmap(wire) could have dupes when checking \init"Eddie Hung2019-10-081-4/+1
| | | | | | | | This reverts commit f46ac1df9f8847dac9d9851f2f948d93a1064ff1.
* | Merge pull request #1432 from YosysHQ/eddie/fix1427Eddie Hung2019-10-084-50/+145
|\ \ | | | | | | Refactor peepopt_dffmux and be sensitive to \init when trimming
| * | Use `sat -tempinduct` and comments for why equiv_opt not sufficientEddie Hung2019-10-031-1/+8
| | |
| * | Fix broken CI, check reset even for constants, trim rstmuxEddie Hung2019-10-022-25/+28
| | |
| * | Fix testEddie Hung2019-10-021-2/+12
| | |
| * | Merge branch 'eddie/fix_sat_init' into eddie/fix1427Eddie Hung2019-10-022-1/+24
| |\ \
| | * | Be mindful that sigmap(wire) could have dupes when checking \initEddie Hung2019-10-021-1/+4
| | | |
| | * | Add test that is expecting to failEddie Hung2019-10-021-0/+20
| | | |
| * | | Update testEddie Hung2019-10-021-13/+3
| | | |
| * | | Refactor peepopt_dffmux and be sensitive to \init when trimmingEddie Hung2019-10-021-32/+63
| | | |
| * | | Add testEddie Hung2019-10-021-0/+31
| | | |
* | | | Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2syncEddie Hung2019-10-083-13/+19
|\ \ \ \ | | | | | | | | | | async2sync to be called by equiv_opt only when -async2sync given
| * | | | Add -async2sync to help text as per @daveshah1Eddie Hung2019-10-041-1/+4
| | | | |
| * | | | Restore part of docEddie Hung2019-10-031-1/+2
| | | | |
| * | | | Disable equiv check for ice40 latchesEddie Hung2019-10-031-6/+3
| | | | |
| * | | | Add new -async2sync optionEddie Hung2019-10-031-1/+11
| | | | |
| * | | | Use equiv_opt -async2sync for xilinxEddie Hung2019-10-031-3/+1
| | | | |
| * | | | Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys"Eddie Hung2019-10-031-2/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit a39505e329cc05dbd4ad624a1cf0f6caf664fd9a.
| * | | | Revert "Update doc for equiv_opt"Eddie Hung2019-10-031-3/+2
| |/ / / | | | | | | | | | | | | This reverts commit a274b7cc86d4f64541d3d2903b4eeed4616ab1d8.
* | | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-0834-309/+316
|\ \ \ \ | | | | | | | | | | Rename abc_* names/attributes to more precisely be abc9_*
| * \ \ \ Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-048-185/+33
| |\ \ \ \
| * | | | | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0434-305/+313
| | | | | |
* | | | | | Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_commentsEddie Hung2019-10-085-72/+364
|\ \ \ \ \ \ | | | | | | | | | | | | | | Add notes and comments for xilinx_dsp
| * | | | | | Missed thisEddie Hung2019-10-051-3/+4
| | | | | | |
| * | | | | | Add comment on why we have to match for clock-enable/reset muxesEddie Hung2019-10-053-3/+11
| | | | | | |
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 13:24:36 +0000