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manual: fix typos.
whitequark
2018-12-20
1
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+2
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manual: document $meminit cell and memory_* passes.
whitequark
2018-12-20
2
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+23
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Merge pull request #758 from whitequark/tcl_script_args
Clifford Wolf
2018-12-21
1
-7
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+18
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tcl: add support for passing arguments to scripts.
whitequark
2018-12-20
1
-7
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+18
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Merge pull request #759 from whitequark/memory_collect_init_x
Clifford Wolf
2018-12-21
1
-3
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memory_collect: do not truncate 'x from \INIT.
whitequark
2018-12-21
1
-3
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Merge pull request #752 from Icenowy/anlogic-lut-cost
Clifford Wolf
2018-12-19
1
-1
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Anlogic: let LUT5/6 have more cost than LUT4-
Icenowy Zheng
2018-12-19
1
-1
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+1
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Merge pull request #753 from Icenowy/anlogic-makefile-fix
Clifford Wolf
2018-12-19
1
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+1
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anlogic: fix Makefile.inc
Icenowy Zheng
2018-12-19
1
-0
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+1
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Merge pull request #749 from Icenowy/anlogic-dram-fix
Clifford Wolf
2018-12-19
1
-1
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anlogic: fix dbits of Anlogic Eagle DRAM16X4
Icenowy Zheng
2018-12-18
1
-1
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+1
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Minor style fixes
Clifford Wolf
2018-12-18
2
-1
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+1
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Merge pull request #748 from makaimann/add-btor-ops
Clifford Wolf
2018-12-18
2
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+38
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Add btor ops for $mul, $div, $mod and $concat
makaimann
2018-12-17
2
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+38
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Merge pull request #751 from daveshah1/fix_589
Clifford Wolf
2018-12-18
1
-1
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+1
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memory_dff: Fix typo when checking init value
David Shah
2018-12-18
1
-1
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+1
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Fix segfault in AST simplify
Clifford Wolf
2018-12-18
1
-0
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+5
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Improve src tagging (using names and attrs) of cells and wires in verific fro...
Clifford Wolf
2018-12-18
2
-99
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+160
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Merge pull request #746 from Icenowy/anlogic-dram
Clifford Wolf
2018-12-17
5
-1
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+355
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anlogic: add support for Eagle Distributed RAM
Icenowy Zheng
2018-12-17
4
-1
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+43
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Revert "Leave only real black box cells"
Icenowy Zheng
2018-12-17
1
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+312
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Merge pull request #742 from whitequark/changelog
Clifford Wolf
2018-12-17
1
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+7
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Update CHANGELOG.
whitequark
2018-12-16
1
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+7
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Merge pull request #741 from whitequark/ilang_slice_sigspec
Clifford Wolf
2018-12-17
1
-10
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+6
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read_ilang: allow slicing sigspecs.
whitequark
2018-12-16
1
-10
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+6
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Merge pull request #744 from whitequark/write_verilog_$shift
Clifford Wolf
2018-12-17
1
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+29
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write_verilog: handle the $shift cell.
whitequark
2018-12-16
1
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+29
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Merge pull request #745 from YosysHQ/revert-714-abc_preserve_naming
Clifford Wolf
2018-12-16
1
-51
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+29
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Revert "Proof-of-concept: preserve naming through ABC using dress"
Clifford Wolf
2018-12-16
1
-51
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+29
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Merge pull request #736 from whitequark/select_assert_list
Clifford Wolf
2018-12-16
2
-9
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+51
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select: print selection if a -assert-* flag causes an error.
whitequark
2018-12-16
1
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+50
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write_verilog: add a missing newline.
whitequark
2018-12-16
1
-1
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+1
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Rename "fine:" label to "map:" in "synth_ice40"
Clifford Wolf
2018-12-16
1
-1
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+1
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Merge pull request #704 from webhat/feature/fix-awk
Clifford Wolf
2018-12-16
1
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+3
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Using awk rather than gawk
Daniƫl W. Crompton
2018-11-19
1
-2
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+3
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Merge pull request #738 from smunaut/issue_737
Clifford Wolf
2018-12-16
1
-19
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+29
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verilog_parser: Properly handle recursion when processing attributes
Sylvain Munaut
2018-12-14
1
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+29
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Merge pull request #735 from daveshah1/trifixes
Clifford Wolf
2018-12-16
1
-3
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+4
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deminout: Consider $tribuf cells
David Shah
2018-12-12
1
-2
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+2
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deminout: Don't demote constant-driven inouts to inputs
David Shah
2018-12-12
1
-1
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+2
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Merge pull request #739 from whitequark/patch-1
Clifford Wolf
2018-12-16
1
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+7
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Add .editorconfig file.
whitequark
2018-12-16
1
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+7
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Fix equiv_opt indenting
Clifford Wolf
2018-12-16
1
-139
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+129
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Merge pull request #724 from whitequark/equiv_opt
Clifford Wolf
2018-12-16
6
-27
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+173
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equiv_opt: pass -D EQUIV when techmapping.
whitequark
2018-12-07
4
-6
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+7
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equiv_opt: new command, for verifying optimization passes.
whitequark
2018-12-07
4
-24
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+169
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Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata
Clifford Wolf
2018-12-16
1
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+17
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memory_bram: Fix initdata bit order after shuffling
Graham Edgecombe
2018-12-11
1
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+17
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Merge pull request #730 from smunaut/ffssr_dont_touch
Clifford Wolf
2018-12-16
1
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+3
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