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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-17 16:35:56 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-17 16:35:56 +0100 |
| commit | 3b4290a1b822aca42ceab4a89043329cb060325d (patch) | |
| tree | bf87175c18089f356fd58fb44f31a877fdffca6f | |
| parent | 97b49d6e4532e7bfd183c8d87113e4993b246b77 (diff) | |
| parent | 9f5c7017ff89ad914b6b9be0620996d77e24f71b (diff) | |
| download | yosys-3b4290a1b822aca42ceab4a89043329cb060325d.tar.gz yosys-3b4290a1b822aca42ceab4a89043329cb060325d.tar.bz2 yosys-3b4290a1b822aca42ceab4a89043329cb060325d.zip | |
Merge pull request #742 from whitequark/changelog
Update CHANGELOG to mention my improvements
| -rw-r--r-- | CHANGELOG | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -9,6 +9,13 @@ Yosys 0.8 .. Yosys 0.8-dev * Various - Added $changed support to read_verilog - Added "write_edif -attrprop" + - Added "ice40_unlut" pass + - Added "opt_lut" pass + - Added "synth_ice40 -relut" + - Added "synth_ice40 -noabc" + - Added "gate2lut.v" techmap rule + - Added "rename -src" + - Added "equiv_opt" pass Yosys 0.7 .. Yosys 0.8 |