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* Add skeleton Yosys-Libero igloo2 example projectClifford Wolf2019-01-055-0/+44
* Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
* Merge pull request #777 from mmicko/achronix_cell_sim_fixClifford Wolf2019-01-041-1/+1
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| * Fix cells_sim.v for Achronix FPGAMiodrag Milanovic2019-01-041-1/+1
* | Remove -m32 Verific eval lib build instructionsClifford Wolf2019-01-041-29/+0
* | Merge pull request #776 from mmicko/unify_noflattenClifford Wolf2019-01-044-8/+16
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| * | Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-044-8/+16
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* / Update Verific default pathClifford Wolf2019-01-041-1/+1
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* Merge pull request #775 from whitequark/opt_flowmapClifford Wolf2019-01-033-1/+875
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| * flowmap: new techmap pass.whitequark2019-01-033-1/+875
* | Merge pull request #770 from whitequark/opt_expr_cmpClifford Wolf2019-01-023-97/+178
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| * opt_expr: improve simplification of comparisons with large constants.whitequark2019-01-022-70/+65
| * opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.whitequark2019-01-022-31/+42
| * opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.whitequark2019-01-022-32/+40
| * opt_expr: simplify any unsigned comparisons with all-0 and all-1.whitequark2019-01-023-17/+84
* | Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
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| * | anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
* | | Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2019-01-0211-35/+256
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| * \ \ Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-023-17/+45
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| | * | | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
| | * | | Add "dffinit -noreinit" parameterIcenowy Zheng2018-12-181-1/+14
| | * | | Add "dffinit -strinit high low"Icenowy Zheng2018-12-181-2/+16
| * | | | Merge pull request #773 from whitequark/opt_lut_elim_fixesClifford Wolf2019-01-021-8/+31
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| | * | | | opt_lut: reflect changes in sigmap.whitequark2019-01-021-0/+2
| | * | | | opt_lut: use a worklist, and revisit cells affected by elimination.whitequark2019-01-021-3/+10
| | * | | | opt_lut: count eliminated cells, and set opt.did_something for them.whitequark2019-01-021-6/+20
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| * | | | Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-022-7/+41
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| | * | | | synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
| | * | | | synth: add k-LUT mode.whitequark2019-01-021-2/+36
| | * | | | synth: improve script documentation. NFC.whitequark2019-01-021-6/+6
| * | | | | Merge pull request #771 from whitequark/techmap_cmp2lutClifford Wolf2019-01-025-3/+139
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| | * | | | cmp2lut: new techmap pass.whitequark2019-01-025-3/+139
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* | / / / Improve VerificImporter support for writes to asymmetric memoriesClifford Wolf2019-01-021-22/+35
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* | | | Fix VerificImporter asymmetric memories error messageClifford Wolf2019-01-021-1/+1
* | | | Merge pull request #769 from whitequark/typosClifford Wolf2019-01-0240-74/+74
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| * | | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-0240-74/+74
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* | | Merge pull request #768 from whitequark/opt_lut_elimClifford Wolf2019-01-014-0/+104
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| * | | opt_lut: eliminate LUTs evaluating to constants or inputs.whitequark2018-12-314-0/+104
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* | | Fix handling of (* keep *) wires in wreduceClifford Wolf2018-12-311-1/+4
* | | Merge pull request #766 from Icenowy/anlogic-latchesClifford Wolf2018-12-311-0/+12
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| * | | anlogic: add latch cellsIcenowy Zheng2018-12-251-0/+12
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* | | Fix 7 instances of add_share_file to add_gen_share_fileLarry Doolittle2018-12-291-8/+8
* | | Squelch a little more trailing whitespaceLarry Doolittle2018-12-292-4/+4
* | | Merge pull request #761 from whitequark/proc_clean_partialClifford Wolf2018-12-233-10/+42
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| * | | proc_clean: remove any empty cases if all cases use all-def compare.whitequark2018-12-233-6/+42
| * | | proc_clean: remove any empty cases at the end of the switch.whitequark2018-12-221-7/+3
* | | | Add "read_ilang -[no]overwrite"Clifford Wolf2018-12-233-4/+54
* | | | Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2018-12-237-22/+58
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| * \ \ \ Merge pull request #757 from whitequark/manual_memClifford Wolf2018-12-222-10/+37
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| | * | | manual: make description of $meminit ports match reality.whitequark2018-12-211-3/+15
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