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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-16 15:53:44 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-16 15:53:44 +0100 |
| commit | a2154c1be0842541d04e2d9e0ebac9ccb3b472be (patch) | |
| tree | 1c6a18f19cfe155b9ad94b698e4c5751ec6b08ca | |
| parent | ceffa66dbd70609184b8e0e82b61442f020811bf (diff) | |
| parent | 4fef9689abb81286af4d9c6bc420b78f61d89550 (diff) | |
| download | yosys-a2154c1be0842541d04e2d9e0ebac9ccb3b472be.tar.gz yosys-a2154c1be0842541d04e2d9e0ebac9ccb3b472be.tar.bz2 yosys-a2154c1be0842541d04e2d9e0ebac9ccb3b472be.zip | |
Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata
memory_bram: Fix initdata bit order after shuffling
| -rw-r--r-- | passes/memory/memory_bram.cc | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 8740042c4..cf4095d06 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -472,8 +472,12 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, std::vector<SigSpec> new_wr_en(GetSize(old_wr_en)); std::vector<SigSpec> new_wr_data(GetSize(old_wr_data)); std::vector<SigSpec> new_rd_data(GetSize(old_rd_data)); + std::vector<std::vector<State>> new_initdata; std::vector<int> shuffle_map; + if (cell_init) + new_initdata.resize(mem_size); + for (auto &it : en_order) { auto &bits = bits_wr_en.at(it); @@ -489,6 +493,10 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, } for (int j = 0; j < rd_ports; j++) new_rd_data[j].append(old_rd_data[j][bits[i]]); + if (cell_init) { + for (int j = 0; j < mem_size; j++) + new_initdata[j].push_back(initdata[j][bits[i]]); + } shuffle_map.push_back(bits[i]); } @@ -499,6 +507,10 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, } for (int j = 0; j < rd_ports; j++) new_rd_data[j].append(State::Sx); + if (cell_init) { + for (int j = 0; j < mem_size; j++) + new_initdata[j].push_back(State::Sx); + } shuffle_map.push_back(-1); } } @@ -522,6 +534,11 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, for (int i = 0; i < rd_ports; i++) rd_data.replace(i*mem_width, new_rd_data[i]); + + if (cell_init) { + for (int i = 0; i < mem_size; i++) + initdata[i] = Const(new_initdata[i]); + } } // assign write ports |