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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-20
31
-50
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+250
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Fix typo, fixes #1095
Clifford Wolf
2019-06-20
1
-1
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+1
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Improve shregmap help message, fixes #1113
Clifford Wolf
2019-06-20
1
-0
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+2
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Update some .gitignore files
Clifford Wolf
2019-06-20
2
-3
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+3
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Fix typo
Clifford Wolf
2019-06-20
1
-2
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+2
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Merge branch 'towoe-unpacked_arrays'
Clifford Wolf
2019-06-20
2
-1
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+23
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Add proper test for SV-style arrays
Clifford Wolf
2019-06-20
3
-6
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+16
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Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo...
Clifford Wolf
2019-06-20
3
-1
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+13
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Unpacked array declaration using size
Tobias Wölfel
2019-06-19
3
-1
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+13
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Merge pull request #1111 from acw1251/help_summary_fixes
Eddie Hung
2019-06-19
4
-6
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+6
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Fixed small typo in ice40_unlut help summary
acw1251
2019-06-19
1
-1
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+1
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Fixed the help summary line for a few commands
acw1251
2019-06-19
4
-6
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+6
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Fix bug in #1078, add entry to CHANGELOG
Eddie Hung
2019-06-19
2
-3
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+4
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Merge pull request #1109 from YosysHQ/clifford/fix1106
Clifford Wolf
2019-06-19
6
-9
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+48
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Add "read_verilog -pwires" feature, closes #1106
Clifford Wolf
2019-06-19
6
-9
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+48
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Merge pull request #1105 from YosysHQ/clifford/fixlogicinit
Clifford Wolf
2019-06-19
5
-16
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+92
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Add defvalue test, minor autotest fixes for .sv files
Clifford Wolf
2019-06-19
2
-14
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+37
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Use input default values in hierarchy pass
Clifford Wolf
2019-06-19
1
-0
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+38
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Add defaultvalue attribute
Clifford Wolf
2019-06-19
2
-0
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+15
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Fix handling of "logic" variables with initial value
Clifford Wolf
2019-06-19
1
-2
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+2
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Make tests/aiger less chatty
Clifford Wolf
2019-06-19
1
-4
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+6
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Merge pull request #1100 from bwidawsk/home
Clifford Wolf
2019-06-19
5
-0
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+8
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Support filename rewrite in backends
Ben Widawsky
2019-06-18
4
-0
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+4
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Support ~ for home directory
Ben Widawsky
2019-06-18
1
-0
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+4
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Merge pull request #1104 from whitequark/case-semantics
Clifford Wolf
2019-06-19
2
-1
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+40
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Explain exact semantics of switch and case rules in the manual.
whitequark
2019-06-19
1
-0
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+12
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In RTLIL::Module::check(), check process invariants.
whitequark
2019-06-19
1
-1
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+28
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Merge pull request #1086 from udif/pr_elab_sys_tasks2
Clifford Wolf
2019-06-18
2
-3
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+13
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Fixed brojen $error()/$info/$warning() on non-generate blocks
Udi Finkelstein
2019-06-11
2
-3
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+13
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Add timescale and generated-by header to yosys-smtbmc MkVcd
Clifford Wolf
2019-06-16
1
-0
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+2
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Fix issue with part of PI being 1'bx
Eddie Hung
2019-06-20
2
-4
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+11
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Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
Eddie Hung
2019-06-20
1
-0
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+1
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Handle COs driven by 1'bx
Eddie Hung
2019-06-20
1
-3
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+9
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Do not call "setundef -zero" in abc9
Eddie Hung
2019-06-20
1
-5
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+2
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write_xaiger to skip POs driven by 1'bx
Eddie Hung
2019-06-20
1
-3
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+7
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Really permute Xilinx LUT mappings as default LUT6.I5:A6
Eddie Hung
2019-06-18
1
-16
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+16
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Revert "Fix (do not) permute LUT inputs, but permute mux selects"
Eddie Hung
2019-06-18
1
-33
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+31
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Clean up
Eddie Hung
2019-06-18
1
-6
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+4
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Fix (do not) permute LUT inputs, but permute mux selects
Eddie Hung
2019-06-18
1
-31
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+33
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Fix copy-pasta issue
Eddie Hung
2019-06-17
1
-9
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+8
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Permute INIT for +/xilinx/lut_map.v
Eddie Hung
2019-06-17
1
-32
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+58
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Simplify comment
Eddie Hung
2019-06-17
1
-1
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+1
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Update LUT7/8 delays to take account for [ABC]OUTMUX delay
Eddie Hung
2019-06-17
1
-5
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+5
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&scorr before &sweep, remove &retime as recommended
Eddie Hung
2019-06-17
1
-1
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+1
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Copy not move parameters/attributes
Eddie Hung
2019-06-17
1
-3
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+4
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Fix leak removing cells during ABC integration; also preserve attr
Eddie Hung
2019-06-17
3
-27
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+37
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Try -W 300
Eddie Hung
2019-06-17
1
-1
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+2
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Re-enable &dc2
Eddie Hung
2019-06-17
1
-1
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+1
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Cleanup
Eddie Hung
2019-06-16
3
-299
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+33
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Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O
Eddie Hung
2019-06-15
1
-2
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+2
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