iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	travis: Reworking travis setup.	Tim 'mithro' Ansell	2017-11-24	5	-33/+262
\| \| \| \| \| \| \| \| \|	* Move the code into scripts inside .travis directory. * Build on multiple compiler versions. Fixes #442 - Make travis build pass Fixes #441 - Fix git version information on travis build Fixes #440 - Make travis cache the iverilog build
*	Use separate writer thread for talking to SMT solver to avoid read/write ↵	Clifford Wolf	2017-10-25	1	-8/+23
\| \| \| \|	deadlock
*	Improve p_* functions in smtio.py	Clifford Wolf	2017-10-25	1	-21/+19
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*	Disable OSX in .travis.yml	Clifford Wolf	2017-10-25	1	-2/+2
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*	Add ENABLE_DEBUG config flag	Clifford Wolf	2017-10-25	1	-1/+10
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*	Update ABC to hg rev f6838749f234	Clifford Wolf	2017-10-25	1	-1/+1
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*	Remove vhdl2verilog	Clifford Wolf	2017-10-25	2	-184/+0
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*	Capsulate smt-solver read/write in separate functions	Clifford Wolf	2017-10-25	1	-8/+24
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*	Fix a bug in yosys-smtbmc in ROM handling	Clifford Wolf	2017-10-25	1	-0/+3
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*	Remove PSL example from tests/sva/	Clifford Wolf	2017-10-20	2	-35/+1
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*	Remove all PSL support code from verific.cc	Clifford Wolf	2017-10-20	1	-179/+17
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*	Merge pull request #437 from mithro/master	Clifford Wolf	2017-10-20	2	-1/+14
\|\ \| \| \| \|	Adding COPYING file with license information.
\| *	Adding COPYING file with license information.	Tim 'mithro' Ansell	2017-10-19	2	-1/+14
\|/ \| \| \| \|	This allows GitHub and other tools to detect the license info. Providing a COPYING for LICENSE file is also pretty standard.
*	Revert 90be0d8 as it causes endless loops for some designs	Clifford Wolf	2017-10-14	1	-1/+0
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*	Add "verific -vlog-libdir"	Clifford Wolf	2017-10-13	1	-0/+12
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*	Add "verific -vlog-incdir" and "verific -vlog-define"	Clifford Wolf	2017-10-13	1	-0/+35
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*	Update Verific README	Clifford Wolf	2017-10-13	1	-0/+7
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*	Merge pull request #434 from Kmanfi/vector_fix	Clifford Wolf	2017-10-12	1	-0/+1
\|\ \| \| \| \|	Fix input vector for reduce cells.
\| *	Fix input vector for reduce cells.	Kaj Tuomi	2017-10-12	1	-0/+1
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* \|	Add Verific fairness/liveness support	Clifford Wolf	2017-10-12	1	-11/+32
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*	Update ABC to hg rev 6283c5d99b06	Clifford Wolf	2017-10-11	1	-1/+1
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2017-10-10	28	-211/+234
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\| *	Rewrite ABC output to include proper net names in timing report	Clifford Wolf	2017-10-10	1	-2/+17
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\| *	Add timing constraints to osu035 example	Clifford Wolf	2017-10-10	3	-2/+4
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\| *	Remove some dead code	Clifford Wolf	2017-10-10	1	-15/+0
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\| *	Allow $past, $stable, $rose, $fell in $global_clock blocks	Clifford Wolf	2017-10-10	1	-1/+5
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\| *	Add $shiftx support to verilog front-end	Clifford Wolf	2017-10-07	1	-0/+17
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\| *	Update ABC to hg rev 0fc1803a77c0	Clifford Wolf	2017-10-06	1	-1/+1
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\| *	Clean whitespace and permissions in techlibs/intel	Larry Doolittle	2017-10-05	21	-190/+190
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* \|	Start work on pre-processor for Verific SVA properties	Clifford Wolf	2017-10-10	1	-10/+153
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*	Improve handling of Verific errors	Clifford Wolf	2017-10-05	1	-11/+9
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*	Improve Verific error handling, check VHDL static asserts	Clifford Wolf	2017-10-04	1	-11/+25
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*	Add blackbox command	Clifford Wolf	2017-10-04	2	-0/+82
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*	Fix nasty bug in Verific bindings	Clifford Wolf	2017-10-04	1	-1/+1
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*	Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys	Clifford Wolf	2017-10-03	2	-14/+14
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\| *	Turned a few member functions into const, esp. dumpAst(), dumpVlog().	Udi Finkelstein	2017-09-30	2	-14/+14
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* \|	Merge branch 'fix_shift_reduce_conflict' of https://github.com/udif/yosys	Clifford Wolf	2017-10-03	1	-3/+5
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\| * \|	Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the ↵	Udi Finkelstein	2017-09-30	1	-3/+5
\| \|/ \| \| \| \| \| \| \| \| \| \|	textbook solution (Oreilly 'Flex & Bison' page 189)
* \|	Merge branch 'dh73-master'	Clifford Wolf	2017-10-03	31	-729/+2965
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\| *	Rename "write_verilog -nobasenradix" to "write_verilog -decimal"	Clifford Wolf	2017-10-03	2	-20/+14
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\| *	Tested and working altsyncarm without init files	dh73	2017-10-01	2	-57/+59
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\| *	Fixed wrong declaration in Verilog backend	dh73	2017-10-01	1	-3/+3
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\| *	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵	dh73	2017-10-01	31	-730/+2970
\|/ \| \| \|	M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
*	Add first draft of eASIC back-end	Clifford Wolf	2017-09-29	2	-0/+191
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*	Fix synth_ice40 doc regarding -top default	Clifford Wolf	2017-09-29	1	-1/+1
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*	Allow $size and $bits in verilog mode, actually check test case	Clifford Wolf	2017-09-29	3	-1/+3
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*	Merge pull request #425 from udif/udif_dollar_bits	Clifford Wolf	2017-09-29	2	-1/+103
\|\ \| \| \| \|	Add $bits() and $size()
\| *	$size() now works correctly for all cases!	Udi Finkelstein	2017-09-26	2	-22/+28
\| \| \| \| \| \| \| \|	It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
\| *	$size() seems to work now with or without the optional parameter.	Udi Finkelstein	2017-09-26	2	-18/+58
\| \| \| \| \| \| \| \|	Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
\| *	enable $bits() and $size() functions only when the SystemVerilog flag is ↵	Udi Finkelstein	2017-09-26	1	-1/+1
\| \| \| \| \| \| \| \|	enabled for read_verilog