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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-29 17:52:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-29 17:52:57 +0200 |
| commit | e64b9d5a4d40ff5a86f35a17ac81786a647726d3 (patch) | |
| tree | cdaf2cea348a2087175a5907c1efa54bafc5cd1f | |
| parent | dbfd8460a9f1d24d1c8893dfae7dd272d17a7b6f (diff) | |
| download | yosys-e64b9d5a4d40ff5a86f35a17ac81786a647726d3.tar.gz yosys-e64b9d5a4d40ff5a86f35a17ac81786a647726d3.tar.bz2 yosys-e64b9d5a4d40ff5a86f35a17ac81786a647726d3.zip | |
Fix synth_ice40 doc regarding -top default
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 2533d3af8..a49372c8a 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -38,7 +38,7 @@ struct SynthIce40Pass : public ScriptPass log("This command runs synthesis for iCE40 FPGAs.\n"); log("\n"); log(" -top <module>\n"); - log(" use the specified module as top module (default='top')\n"); + log(" use the specified module as top module\n"); log("\n"); log(" -blif <file>\n"); log(" write the design to the specified BLIF file. writing of an output file\n"); |