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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-12 12:16:47 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-10-12 12:16:47 +0200 |
| commit | d565bc4a826b45a542699c5d7b085170ef4981b4 (patch) | |
| tree | 92233bad61080460ecbd862a23e94e63904a3e86 | |
| parent | bc5cc4e103bf59711c339719d6aabbc3d4b655a4 (diff) | |
| parent | 90be0d800b350da12689c7943800e18420149eaa (diff) | |
| download | yosys-d565bc4a826b45a542699c5d7b085170ef4981b4.tar.gz yosys-d565bc4a826b45a542699c5d7b085170ef4981b4.tar.bz2 yosys-d565bc4a826b45a542699c5d7b085170ef4981b4.zip | |
Merge pull request #434 from Kmanfi/vector_fix
Fix input vector for reduce cells.
| -rw-r--r-- | passes/opt/opt_reduce.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index eb9d02ad5..10bdf7221 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -88,6 +88,7 @@ struct OptReduceWorker RTLIL::SigSpec new_sig_a(new_sig_a_bits); if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) { + new_sig_a.sort_and_unify(); log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; total_count++; |