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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-07 13:40:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-07 13:40:54 +0200 |
| commit | adf17547290b403e863ed7c71960a5678c6bbfaf (patch) | |
| tree | fbc4a1c5cba91aa23ea455e6dfe002f6db668a3b | |
| parent | 2b04e8caa6043c309cf596ee21e55541b2e2b24c (diff) | |
| download | yosys-adf17547290b403e863ed7c71960a5678c6bbfaf.tar.gz yosys-adf17547290b403e863ed7c71960a5678c6bbfaf.tar.bz2 yosys-adf17547290b403e863ed7c71960a5678c6bbfaf.zip | |
Add $shiftx support to verilog front-end
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index fb0add847..bdf705056 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -678,6 +678,23 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) #undef HANDLE_UNIOP #undef HANDLE_BINOP + if (cell->type == "$shiftx") + { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + f << stringf(" = "); + dump_sigspec(f, cell->getPort("\\A")); + f << stringf("["); + if (cell->getParam("\\B_SIGNED").as_bool()) + f << stringf("$signed("); + dump_sigspec(f, cell->getPort("\\B")); + if (cell->getParam("\\B_SIGNED").as_bool()) + f << stringf(")"); + f << stringf(" +: %d", cell->getParam("\\Y_WIDTH").as_int()); + f << stringf("];\n"); + return true; + } + if (cell->type == "$mux") { f << stringf("%s" "assign ", indent.c_str()); |