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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-14 11:57:04 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-14 11:57:25 +0200 |
| commit | 716dbc92745aa8b41d85a60d50263433d5a79393 (patch) | |
| tree | c4779751b645d6a28881a9bb50653a54518708f8 | |
| parent | 1954c78ea7b6ddc732ac4dc9f02a0d0cbc104a64 (diff) | |
| download | yosys-716dbc92745aa8b41d85a60d50263433d5a79393.tar.gz yosys-716dbc92745aa8b41d85a60d50263433d5a79393.tar.bz2 yosys-716dbc92745aa8b41d85a60d50263433d5a79393.zip | |
Revert 90be0d8 as it causes endless loops for some designs
| -rw-r--r-- | passes/opt/opt_reduce.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 10bdf7221..eb9d02ad5 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -88,7 +88,6 @@ struct OptReduceWorker RTLIL::SigSpec new_sig_a(new_sig_a_bits); if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) { - new_sig_a.sort_and_unify(); log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; total_count++; |