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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-03 18:20:08 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-03 18:20:08 +0200 |
| commit | 983479f395ca2edade4d538a225a3426a1fcff38 (patch) | |
| tree | 38df368f73cf562332aceec2e722ed73d6e46e98 | |
| parent | b4fd7ecd839af207e8c332d8f37a59b6c0196b9d (diff) | |
| parent | 72a08eca3dd6e7df1094c83afb97a0a293a1117e (diff) | |
| download | yosys-983479f395ca2edade4d538a225a3426a1fcff38.tar.gz yosys-983479f395ca2edade4d538a225a3426a1fcff38.tar.bz2 yosys-983479f395ca2edade4d538a225a3426a1fcff38.zip | |
Merge branch 'fix_shift_reduce_conflict' of https://github.com/udif/yosys
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 9fa2a1a2f..ec92f6628 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -142,7 +142,9 @@ static void free_attr(std::map<std::string, AstNode*> *al) %define parse.error verbose %define parse.lac full -%expect 2 +%nonassoc FAKE_THEN +%nonassoc TOK_ELSE + %debug %% @@ -1261,7 +1263,7 @@ optional_else: ast_stack.back()->children.push_back(cond); ast_stack.push_back(block); } behavioral_stmt | - /* empty */; + /* empty */ %prec FAKE_THEN; case_body: case_body case_item | @@ -1432,7 +1434,7 @@ gen_stmt_or_null: gen_stmt_block | ';'; opt_gen_else: - TOK_ELSE gen_stmt_or_null | /* empty */; + TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN; expr: basic_expr { |