| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | | * | Add generic __builtin_bswap32 function | Eddie Hung | 2019-06-28 | 1 | -0/+15 | |
| | | * | Also fix write_aiger for UB | Eddie Hung | 2019-06-28 | 1 | -26/+26 | |
| | | * | Fix more potential for undefined behaviour due to container invalidation | Eddie Hung | 2019-06-28 | 1 | -6/+10 | |
| | | * | Update synth_ice40 -device doc to be relevant for -abc9 only | Eddie Hung | 2019-06-28 | 1 | -2/+2 | |
| | | * | Disable boxing of ECP5 dist RAM due to regression | Eddie Hung | 2019-06-28 | 1 | -1/+1 | |
| | | * | Add write address to abc_scc_break of ECP5 dist RAM | Eddie Hung | 2019-06-28 | 1 | -1/+1 | |
| | | * | Fix DO4 typo | Eddie Hung | 2019-06-28 | 1 | -1/+1 | |
| | | * | Reduce diff with upstream | Eddie Hung | 2019-06-27 | 1 | -4/+2 | |
| | | * | Extraneous newline | Eddie Hung | 2019-06-27 | 1 | -1/+0 | |
| | | * | Remove noise from ice40/cells_sim.v | Eddie Hung | 2019-06-27 | 1 | -5/+0 | |
| | | * | Refactor for one "abc_carry" attribute on module | Eddie Hung | 2019-06-27 | 5 | -82/+84 | |
| | | * | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-06-27 | 2 | -0/+19 | |
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| | | | * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-27 | 2 | -0/+19 | |
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| | | * | | | Do not use Module::remove() iterator version | Eddie Hung | 2019-06-27 | 1 | -5/+6 | |
| | | * | | | Remove redundant doc | Eddie Hung | 2019-06-27 | 1 | -3/+0 | |
| | | * | | | Remove &retime when abc9 -fast | Eddie Hung | 2019-06-27 | 1 | -1/+1 | |
| | | * | | | Cleanup abc9.cc | Eddie Hung | 2019-06-27 | 1 | -15/+17 | |
| | | * | | | Undo iterator based Module::remove() for cells, as containers will not | Eddie Hung | 2019-06-27 | 2 | -11/+2 | |
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| | * | | | Merge pull request #1146 from gsomlo/gls-test-abc-ext | Clifford Wolf | 2019-06-28 | 4 | -8/+29 | |
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| | | * | | | tests: use optional ABCEXTERNAL when specified | Gabriel L. Somlo | 2019-06-27 | 4 | -8/+29 | |
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| | * | | | Merge pull request #1046 from bogdanvuk/master | Clifford Wolf | 2019-06-28 | 5 | -16/+127 | |
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| | | * | | Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too | Bogdan Vukobratovic | 2019-06-27 | 2 | -2/+10 | |
| | | * | | Fix memory leak when one of multiple DFF cells is removed in opt_rmdff | Bogdan Vukobratovic | 2019-06-27 | 1 | -0/+5 | |
| | | * | | Merge remote-tracking branch 'upstream/master' | Bogdan Vukobratovic | 2019-06-27 | 37 | -143/+1631 | |
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| | | * | | | Refactor "opt_rmdff -sat" | Clifford Wolf | 2019-06-20 | 4 | -373/+58 | |
| | | * | | | Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext... | Clifford Wolf | 2019-06-20 | 5 | -10/+423 | |
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| | | | * | | | Move netlist helper module to passes/opt for the time being | Bogdan Vukobratovic | 2019-06-14 | 2 | -1/+1 | |
| | | | * | | | Merge remote-tracking branch 'upstream/master' | Bogdan Vukobratovic | 2019-06-14 | 73 | -475/+1352 | |
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| | | | * | | | | Prepare for situation when port of the signal cannot be found | Bogdan Vukobratovic | 2019-06-14 | 2 | -2/+8 | |
| | | | * | | | | Some cleanup, revert sat.cc | Bogdan Vukobratovic | 2019-06-14 | 2 | -13/+11 | |
| | | | * | | | | Implement disconnection of constant register bits | Bogdan Vukobratovic | 2019-06-13 | 2 | -44/+109 | |
| | | | * | | | | Pass SigBit by value to Netlist algorithms | Bogdan Vukobratovic | 2019-06-13 | 1 | -65/+84 | |
| | | | * | | | | Rename satgen_algo.h -> algo.h, code cleanup and refactoring | Bogdan Vukobratovic | 2019-06-12 | 4 | -279/+265 | |
| | | | * | | | | Generate satgen instance instead of calling sat pass | Bogdan Vukobratovic | 2019-06-11 | 2 | -24/+129 | |
| | | | * | | | | Refactor driver map generation | Bogdan Vukobratovic | 2019-06-10 | 1 | -0/+158 | |
| | | | * | | | | Fix the regression | Bogdan Vukobratovic | 2019-05-28 | 1 | -1/+2 | |
| | | | * | | | | Merge remote-tracking branch 'upstream/master' | Bogdan Vukobratovic | 2019-05-28 | 1 | -1/+11 | |
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| | | | * | | | | | Optimizing DFFs whose initial value prevents their value from changing | Bogdan Vukobratovic | 2019-05-28 | 4 | -3/+78 | |
| | * | | | | | | | Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog | Eddie Hung | 2019-06-27 | 2 | -0/+19 | |
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| | | * | | | | | | | Add simcells.v, simlib.v, and some output | Eddie Hung | 2019-06-27 | 1 | -1/+11 | |
| | | * | | | | | | | tests: Check that Icarus can parse arch sim models | David Shah | 2019-06-26 | 2 | -0/+9 | |
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| * | | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-06-27 | 4 | -9/+39 | |
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| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-27 | 4 | -9/+39 | |
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| | | * | | | | | | Grr | Eddie Hung | 2019-06-27 | 1 | -1/+1 | |
| | | * | | | | | | Capitalisation | Eddie Hung | 2019-06-27 | 1 | -1/+1 | |
| | | * | | | | | | Make CHANGELOG clearer | Eddie Hung | 2019-06-27 | 1 | -0/+1 | |
| | | * | | | | | | Merge pull request #1143 from YosysHQ/clifford/fix1135 | Eddie Hung | 2019-06-27 | 4 | -8/+38 | |
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| | | | * | | | | | | Add #1135 testcase | Eddie Hung | 2019-06-27 | 2 | -5/+26 | |
| | | | * | | | | | | Add "pmux2shiftx -norange", fixes #1135 | Clifford Wolf | 2019-06-27 | 2 | -3/+12 | |
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| * | | | | | | | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-27 | 0 | -0/+0 | |
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