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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 11:26:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 11:50:12 -0700 |
| commit | 36f3cc9dcc07fc8a0c718fa0611ec39fd267900b (patch) | |
| tree | e61d5bd845ca6db8c891f654e3e8b4dfce1642e8 | |
| parent | d5cfe341f9a2d8decbef1b59617f51ae6369f0a4 (diff) | |
| download | yosys-36f3cc9dcc07fc8a0c718fa0611ec39fd267900b.tar.gz yosys-36f3cc9dcc07fc8a0c718fa0611ec39fd267900b.tar.bz2 yosys-36f3cc9dcc07fc8a0c718fa0611ec39fd267900b.zip | |
Capitalisation
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -47,7 +47,7 @@ Yosys 0.7 .. Yosys 0.8 - Added Verilog $rtoi and $itor support - Added "check -initdrv" - Added "read_blif -wideports" - - Added support for systemVerilog "++" and "--" operators + - Added support for SystemVerilog "++" and "--" operators - Added support for SystemVerilog unique, unique0, and priority case - Added "write_edif" options for edif "flavors" - Added support for resetall compiler directive |