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| * greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)Andrew Zonenberg2016-08-131-10/+10
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* Merge pull request #198 from whitequark/masterClifford Wolf2016-08-111-0/+2
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| * synth_greenpak4: use attrmvcp to move LOC from wires to cells.whitequark2016-08-101-0/+2
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* Only allow posedge/negedge with 1 bit wide signalsClifford Wolf2016-08-101-0/+2
* Fixed some compiler warnings in attrmap commandClifford Wolf2016-08-101-4/+4
* Added "attrmap" commandClifford Wolf2016-08-093-0/+253
* Added log_const() APIClifford Wolf2016-08-092-0/+19
* Added "attrmvcp" passClifford Wolf2016-08-092-0/+138
* Use /proc/self/exe on Cygwin as well.Yury Gribov2016-08-081-1/+1
* Undo "preserve wire attributes in iopadmap" change (it was OK before)Clifford Wolf2016-08-081-1/+1
* Added "test_autotb -seed" (and "autotest.sh -S")Clifford Wolf2016-08-062-5/+12
* preserve wire attributes in iopadmapClifford Wolf2016-08-061-1/+1
* Fixed bug in parsing real constantsClifford Wolf2016-08-061-4/+4
* Added "insbuf" commandClifford Wolf2016-08-022-0/+95
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-07-3016-22/+162
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| * Added $initstate support to smtbmc flowClifford Wolf2016-07-273-2/+19
| * Added SatGen support for $anyconstClifford Wolf2016-07-271-0/+22
| * Removed $predict support from SatGenClifford Wolf2016-07-271-9/+0
| * Added $anyconst and $aconstClifford Wolf2016-07-277-2/+83
| * Added "read_verilog -dump_rtlil"Clifford Wolf2016-07-275-9/+38
* | Added "write_verilog -defparam"Clifford Wolf2016-07-301-2/+21
* | Added "write_verilog -nodec -nostr"Clifford Wolf2016-07-301-4/+27
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* Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()Clifford Wolf2016-07-253-3/+3
* Fixed a verilog parser memory leakClifford Wolf2016-07-251-0/+1
* Fixed parsing of empty positional cell portsClifford Wolf2016-07-251-2/+31
* Improvements in CellEdgesDatabaseClifford Wolf2016-07-243-16/+167
* Added CellEdgesDatabase APIClifford Wolf2016-07-244-1/+250
* Moved SatHelper::setup_init() code to SatHelper::setup()Clifford Wolf2016-07-241-97/+92
* Added $initstate support to "sat" commandClifford Wolf2016-07-231-13/+12
* No tristate warning message for "read_verilog -lib"Clifford Wolf2016-07-233-8/+11
* Added satgen initstate supportClifford Wolf2016-07-221-0/+27
* Using $initstate in "initial assume" and "initial assert"Clifford Wolf2016-07-211-1/+6
* Added $initstate cell type and vlog functionClifford Wolf2016-07-217-4/+54
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-2116-32/+28
* Added basic support for $expect cellsClifford Wolf2016-07-1316-19/+82
* Added examples/smtbmcClifford Wolf2016-07-132-0/+30
* Merge pull request #191 from whitequark/json-module-attributesClifford Wolf2016-07-131-2/+6
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| * write_json: also write module attributes.whitequark2016-07-121-2/+6
* | Merge pull request #193 from azonenberg/masterClifford Wolf2016-07-132-2/+9
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| * \ Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-07-121-2/+5
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* | | Minor bugfix in FSM reset state detectionClifford Wolf2016-07-121-2/+5
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| * Added GP_DAC cellAndrew Zonenberg2016-07-111-0/+8
| * Removed VOUT port of GP_BANDGAPAndrew Zonenberg2016-07-111-1/+1
| * Removed splitnets in prep for new gp4par parserAndrew Zonenberg2016-07-111-1/+0
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* Yosys-smtbmc: Support for hierarchical VCD dumpingClifford Wolf2016-07-112-23/+59
* Moved smt2 yosys info parsing from smtbmc.py to smtio.pyClifford Wolf2016-07-113-16/+56
* Added "prep -auto-top" and "synth -auto-top"Clifford Wolf2016-07-112-6/+23
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-07-101-0/+26
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| * Merge pull request #189 from whitequark/masterClifford Wolf2016-07-101-0/+26
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| | * greenpak4: add GP_COUNT{8,14}_ADV cells.whitequark2016-07-101-0/+26
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