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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-25 16:37:58 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-25 16:37:58 +0200 |
| commit | 5b944ef11b8964a00d833ad29c96ad46da06f7a3 (patch) | |
| tree | c57f4ff5b90e1a8282cccac62df26597f25164d5 | |
| parent | 7a67add95d3d2f3293f84e38b891024d6444d2a4 (diff) | |
| download | yosys-5b944ef11b8964a00d833ad29c96ad46da06f7a3.tar.gz yosys-5b944ef11b8964a00d833ad29c96ad46da06f7a3.tar.bz2 yosys-5b944ef11b8964a00d833ad29c96ad46da06f7a3.zip | |
Fixed a verilog parser memory leak
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index d1da630d5..4cb65a088 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -880,6 +880,7 @@ cell_port_list: if (!node->children.empty()) break; if (!node->str.empty()) break; astbuf2->children.pop_back(); + delete node; } // check port types |