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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-07-11 22:45:42 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-07-11 22:45:42 -0700 |
| commit | baae472b83b3dac1293bb95ff0a87d9180a67479 (patch) | |
| tree | a341ef6ddbbb13f5189d131af70b3ff4dd7abf2d | |
| parent | 8619d33114edc58d89247ac3471d4115e1689a82 (diff) | |
| download | yosys-baae472b83b3dac1293bb95ff0a87d9180a67479.tar.gz yosys-baae472b83b3dac1293bb95ff0a87d9180a67479.tar.bz2 yosys-baae472b83b3dac1293bb95ff0a87d9180a67479.zip | |
Removed VOUT port of GP_BANDGAP
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 67f00f3a4..bf178a08a 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -36,7 +36,7 @@ module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT endmodule -module GP_BANDGAP(output reg OK, output reg VOUT); +module GP_BANDGAP(output reg OK); parameter AUTO_PWRDN = 1; parameter CHOPPER_EN = 1; parameter OUT_DELAY = 100; |