Improvements in CellEdgesDatabase

3 files changed, 167 insertions, 16 deletions

diff --git a/kernel/celledges.cc b/kernel/celledges.cc
index b6786b116..430425ea8 100644
--- a/kernel/celledges.cc
+++ b/kernel/celledges.cc
@@ -22,7 +22,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-void add_bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
 	IdString A = "\\A", Y = "\\Y";
 
@@ -33,13 +33,13 @@ void add_bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 	for (int i = 0; i < y_width; i++)
 	{
 		if (i < a_width)
-			db->add_edge(cell, A, i, Y, i);
+			db->add_edge(cell, A, i, Y, i, -1);
 		else if (is_signed && a_width > 0)
-			db->add_edge(cell, A, a_width-1, Y, i);
+			db->add_edge(cell, A, a_width-1, Y, i, -1);
 	}
 }
 
-void add_bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
 	IdString A = "\\A", B = "\\B", Y = "\\Y";
 
@@ -58,14 +58,101 @@ void add_bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 	for (int i = 0; i < y_width; i++)
 	{
 		if (i < a_width)
-			db->add_edge(cell, A, i, Y, i);
+			db->add_edge(cell, A, i, Y, i, -1);
 		else if (is_signed && a_width > 0)
-			db->add_edge(cell, A, a_width-1, Y, i);
+			db->add_edge(cell, A, a_width-1, Y, i, -1);
 
 		if (i < b_width)
-			db->add_edge(cell, B, i, Y, i);
+			db->add_edge(cell, B, i, Y, i, -1);
 		else if (is_signed && b_width > 0)
-			db->add_edge(cell, B, b_width-1, Y, i);
+			db->add_edge(cell, B, b_width-1, Y, i, -1);
+	}
+}
+
+void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+{
+	IdString A = "\\A", Y = "\\Y";
+
+	bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
+	int a_width = GetSize(cell->getPort(A));
+	int y_width = GetSize(cell->getPort(Y));
+
+	if (is_signed && a_width == 1)
+		y_width = std::min(y_width, 1);
+
+	for (int i = 0; i < y_width; i++)
+	for (int k = 0; k <= i && k < a_width; k++)
+		db->add_edge(cell, A, k, Y, i, -1);
+}
+
+void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+{
+	IdString A = "\\A", B = "\\B", Y = "\\Y";
+
+	bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
+	int a_width = GetSize(cell->getPort(A));
+	int b_width = GetSize(cell->getPort(B));
+	int y_width = GetSize(cell->getPort(Y));
+
+	if (!is_signed && cell->type != "$sub") {
+		int ab_width = std::max(a_width, b_width);
+		y_width = std::min(y_width, ab_width+1);
+	}
+
+	for (int i = 0; i < y_width; i++)
+	{
+		for (int k = 0; k <= i; k++)
+		{
+			if (k < a_width)
+				db->add_edge(cell, A, k, Y, i, -1);
+
+			if (k < b_width)
+				db->add_edge(cell, B, k, Y, i, -1);
+		}
+	}
+}
+
+void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+{
+	IdString A = "\\A", Y = "\\Y";
+
+	int a_width = GetSize(cell->getPort(A));
+
+	for (int i = 0; i < a_width; i++)
+		db->add_edge(cell, A, i, Y, 0, -1);
+}
+
+void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+{
+	IdString A = "\\A", B = "\\B", Y = "\\Y";
+
+	int a_width = GetSize(cell->getPort(A));
+	int b_width = GetSize(cell->getPort(B));
+
+	for (int i = 0; i < a_width; i++)
+		db->add_edge(cell, A, i, Y, 0, -1);
+
+	for (int i = 0; i < b_width; i++)
+		db->add_edge(cell, B, i, Y, 0, -1);
+}
+
+void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+{
+	IdString A = "\\A", B = "\\B", S = "\\S", Y = "\\Y";
+
+	int a_width = GetSize(cell->getPort(A));
+	int b_width = GetSize(cell->getPort(B));
+	int s_width = GetSize(cell->getPort(S));
+
+	for (int i = 0; i < a_width; i++)
+	{
+		db->add_edge(cell, A, i, Y, i, -1);
+
+		for (int k = i; k < b_width; k += a_width)
+			db->add_edge(cell, B, k, Y, i, -1);
+
+		for (int k = 0; k < s_width; k++)
+			db->add_edge(cell, S, k, Y, i, -1);
 	}
 }
 
@@ -74,15 +161,49 @@ PRIVATE_NAMESPACE_END
 bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_cell(RTLIL::Cell *cell)
 {
 	if (cell->type.in("$not", "$pos")) {
-		add_bitwise_unary_op(this, cell);
+		bitwise_unary_op(this, cell);
 		return true;
 	}
 
 	if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
-		add_bitwise_binary_op(this, cell);
+		bitwise_binary_op(this, cell);
 		return true;
 	}
 
+	if (cell->type == "$neg") {
+		arith_neg_op(this, cell);
+		return true;
+	}
+
+	if (cell->type.in("$add", "$sub")) {
+		arith_binary_op(this, cell);
+		return true;
+	}
+
+	if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", "$logic_not")) {
+		reduce_op(this, cell);
+		return true;
+	}
+
+	// FIXME:
+	// if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
+	// 	shift_op(this, cell);
+	// 	return true;
+	// }
+
+	if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
+		compare_op(this, cell);
+		return true;
+	}
+
+	if (cell->type.in("$mux", "$pmux")) {
+		mux_op(this, cell);
+		return true;
+	}
+
+	// FIXME: $mul $div $mod $slice $concat
+	// FIXME: $lut $sop $alu $lcu $macc $fa
+
 	return false;
 }
 
diff --git a/kernel/celledges.h b/kernel/celledges.h
index fe863766c..e2cc408d7 100644
--- a/kernel/celledges.h
+++ b/kernel/celledges.h
@@ -28,7 +28,7 @@ YOSYS_NAMESPACE_BEGIN
 struct AbstractCellEdgesDatabase
 {
 	virtual ~AbstractCellEdgesDatabase() { }
-	virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) = 0;
+	virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0;
 	bool add_cell(RTLIL::Cell *cell);
 };
 
@@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
 	dict<SigBit, pool<SigBit>> db;
 	FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
 
-	virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) override {
+	virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
 		SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
 		SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
 		db[from_sigbit].insert(to_sigbit);
@@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase
 	dict<SigBit, pool<SigBit>> db;
 	RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
 
-	virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) override {
+	virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
 		SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
 		SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
 		db[to_sigbit].insert(from_sigbit);
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 5a47634ac..8e9dc3112 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -43,6 +43,32 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 	RTLIL::Cell *cell = module->addCell("\\UUT", cell_type);
 	RTLIL::Wire *wire;
 
+	if (cell_type == "$mux" || cell_type == "$pmux")
+	{
+		int width = 1 + xorshift32(8);
+		int swidth = cell_type == "$mux" ? 1 : 1 + xorshift32(8);
+
+		wire = module->addWire("\\A");
+		wire->width = width;
+		wire->port_input = true;
+		cell->setPort("\\A", wire);
+
+		wire = module->addWire("\\B");
+		wire->width = width * swidth;
+		wire->port_input = true;
+		cell->setPort("\\B", wire);
+
+		wire = module->addWire("\\S");
+		wire->width = swidth;
+		wire->port_input = true;
+		cell->setPort("\\S", wire);
+
+		wire = module->addWire("\\Y");
+		wire->width = width;
+		wire->port_output = true;
+		cell->setPort("\\Y", wire);
+	}
+
 	if (cell_type == "$fa")
 	{
 		int width = 1 + xorshift32(8);
@@ -318,7 +344,8 @@ static void run_edges_test(RTLIL::Design *design, bool verbose)
 	SatGen satgen(&ez, &sigmap);
 
 	FwdCellEdgesDatabase edges_db(sigmap);
-	edges_db.add_cell(cell);
+	if (!edges_db.add_cell(cell))
+		log_error("Creating edge database failed for this cell!\n");
 
 	dict<SigBit, pool<SigBit>> satgen_db;
 
@@ -818,8 +845,11 @@ struct TestCellPass : public Pass {
 		cell_types["$logic_and"] = "ABSY";
 		cell_types["$logic_or"]  = "ABSY";
 
-		// cell_types["$mux"] = "A";
-		// cell_types["$pmux"] = "A";
+		if (edges) {
+			cell_types["$mux"] = "*";
+			cell_types["$pmux"] = "*";
+		}
+
 		// cell_types["$slice"] = "A";
 		// cell_types["$concat"] = "A";
 		// cell_types["$assert"] = "A";