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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-25 16:39:25 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-25 16:39:25 +0200 |
| commit | 8537c4d2061db1ee11defc357781c6c534be5b3d (patch) | |
| tree | 4fe2f7e4f7082ee6add823da39910912a52dc6e1 | |
| parent | 5b944ef11b8964a00d833ad29c96ad46da06f7a3 (diff) | |
| download | yosys-8537c4d2061db1ee11defc357781c6c534be5b3d.tar.gz yosys-8537c4d2061db1ee11defc357781c6c534be5b3d.tar.bz2 yosys-8537c4d2061db1ee11defc357781c6c534be5b3d.zip | |
Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
| -rw-r--r-- | kernel/celledges.cc | 2 | ||||
| -rw-r--r-- | kernel/celledges.h | 2 | ||||
| -rw-r--r-- | passes/tests/test_cell.cc | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 430425ea8..556e8b826 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -158,7 +158,7 @@ void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) PRIVATE_NAMESPACE_END -bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_cell(RTLIL::Cell *cell) +bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell) { if (cell->type.in("$not", "$pos")) { bitwise_unary_op(this, cell); diff --git a/kernel/celledges.h b/kernel/celledges.h index e2cc408d7..6aab9ed43 100644 --- a/kernel/celledges.h +++ b/kernel/celledges.h @@ -29,7 +29,7 @@ struct AbstractCellEdgesDatabase { virtual ~AbstractCellEdgesDatabase() { } virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0; - bool add_cell(RTLIL::Cell *cell); + bool add_edges_from_cell(RTLIL::Cell *cell); }; struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 8e9dc3112..19fad01ef 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -344,7 +344,7 @@ static void run_edges_test(RTLIL::Design *design, bool verbose) SatGen satgen(&ez, &sigmap); FwdCellEdgesDatabase edges_db(sigmap); - if (!edges_db.add_cell(cell)) + if (!edges_db.add_edges_from_cell(cell)) log_error("Creating edge database failed for this cell!\n"); dict<SigBit, pool<SigBit>> satgen_db; |