| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Further cleanup based on @daveshah1 | Eddie Hung | 2019-06-14 | 4 | -47/+47 |
| * | Resolve comments from @daveshah1 | Eddie Hung | 2019-06-14 | 3 | -17/+11 |
| * | Add XC7_WIRE_DELAY macro to synth_xilinx.cc | Eddie Hung | 2019-06-14 | 1 | -1/+3 |
| * | Update delays based on SymbiFlow/prjxray-db | Eddie Hung | 2019-06-14 | 1 | -12/+13 |
| * | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut} | Eddie Hung | 2019-06-14 | 4 | -3/+3 |
| * | Comment out dist RAM boxing on ECP5 for now | Eddie Hung | 2019-06-14 | 1 | -1/+1 |
| * | Remove WIP ABC9 flop support | Eddie Hung | 2019-06-14 | 5 | -79/+79 |
| * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-14 | 2 | -0/+46 |
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| | * | Merge pull request #829 from abdelrahmanhosny/master | Serge Bazanski | 2019-06-13 | 2 | -0/+46 |
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| | | * | address review comments | Abdelrahman | 2019-03-01 | 1 | -23/+9 |
| | | * | add dockerignore file | Abdelrahman | 2019-02-26 | 1 | -0/+13 |
| | | * | dockerize yosys | Abdelrahman | 2019-02-26 | 1 | -0/+47 |
| * | | | Make doc consistent | Eddie Hung | 2019-06-14 | 3 | -3/+6 |
| * | | | Cleanup | Eddie Hung | 2019-06-14 | 1 | -1/+0 |
| * | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-06-14 | 8 | -72/+194 |
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| | * \ \ | Merge pull request #1097 from YosysHQ/dave/xaig_ecp5 | Eddie Hung | 2019-06-14 | 8 | -72/+194 |
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| | | * | | | ecp5: Add abc9 option | David Shah | 2019-06-14 | 8 | -72/+194 |
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| * | | | | Cleanup | Eddie Hung | 2019-06-14 | 1 | -7/+3 |
| * | | | | Cleanup/optimise toposort in write_xaiger | Eddie Hung | 2019-06-14 | 1 | -54/+47 |
| * | | | | Remove extra semicolon | Eddie Hung | 2019-06-14 | 1 | -1/+1 |
| * | | | | Add TODO to parse_xaiger | Eddie Hung | 2019-06-14 | 1 | -0/+1 |
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| * | | | Optimise some more | Eddie Hung | 2019-06-13 | 1 | -58/+53 |
| * | | | Move ConstEvalAig to aigerparse.cc | Eddie Hung | 2019-06-13 | 2 | -160/+161 |
| * | | | Fix name clash | Eddie Hung | 2019-06-13 | 1 | -4/+8 |
| * | | | More slimming | Eddie Hung | 2019-06-13 | 1 | -35/+35 |
| * | | | Add ConstEvalAig specialised for AIGs | Eddie Hung | 2019-06-13 | 2 | -3/+159 |
| * | | | Update CHANGELOG with "synth -abc9" | Eddie Hung | 2019-06-13 | 1 | -0/+1 |
| * | | | Fix LP SB_LUT4 timing | Eddie Hung | 2019-06-13 | 1 | -1/+1 |
| * | | | More accurate CHANGELOG | Eddie Hung | 2019-06-13 | 1 | -1/+3 |
| * | | | Update CHANGELOG | Eddie Hung | 2019-06-12 | 1 | -0/+1 |
| * | | | Rip out all non FPGA stuff from abc9 | Eddie Hung | 2019-06-12 | 1 | -343/+111 |
| * | | | Fix spelling | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
| * | | | Revert "For 'stat' do not count modules with abc_box_id" | Eddie Hung | 2019-06-12 | 1 | -3/+0 |
| * | | | Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" | Eddie Hung | 2019-06-12 | 2 | -247/+0 |
| * | | | Move neg-pol to pos-pol mapping from ff_map to cells_map.v | Eddie Hung | 2019-06-12 | 1 | -0/+8 |
| * | | | Be more precise when connecting during ABC9 re-integration | Eddie Hung | 2019-06-12 | 1 | -1/+3 |
| * | | | Remove unnecessary undriven_bits.insert | Eddie Hung | 2019-06-12 | 1 | -4/+1 |
| * | | | Remove hacky wideports_split from abc9 | Eddie Hung | 2019-06-12 | 1 | -52/+4 |
| * | | | Fix compile errors when #if 1 for debug | Eddie Hung | 2019-06-12 | 1 | -7/+8 |
| * | | | parse_xaiger to cope with inouts | Eddie Hung | 2019-06-12 | 1 | -6/+0 |
| * | | | write_xaiger to preserve POs even if driven by constant | Eddie Hung | 2019-06-12 | 1 | -7/+6 |
| * | | | Add a couple more tests | Eddie Hung | 2019-06-12 | 2 | -21/+30 |
| * | | | Do not call abc9 if no outputs | Eddie Hung | 2019-06-12 | 1 | -54/+65 |
| * | | | More write_xaiger cleanup | Eddie Hung | 2019-06-12 | 2 | -41/+13 |
| * | | | Cleanup write_xaiger | Eddie Hung | 2019-06-12 | 1 | -92/+6 |
| * | | | Consistency | Eddie Hung | 2019-06-12 | 4 | -4/+4 |
| * | | | Reduce diff with master | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
| * | | | Remove abc_flop{,_d} attributes from ice40/cells_sim.v | Eddie Hung | 2019-06-12 | 1 | -40/+20 |
| * | | | Fix spacing | Eddie Hung | 2019-06-12 | 1 | -6/+6 |
| * | | | Remove wide mux inference | Eddie Hung | 2019-06-12 | 5 | -195/+3 |
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index : iCE40/yosys | |
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