aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--backends/aiger/xaiger.cc48
-rw-r--r--frontends/aiger/aigerparse.cc30
-rw-r--r--kernel/rtlil.h6
-rw-r--r--passes/techmap/abc9.cc10
4 files changed, 47 insertions, 47 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 42a2233e4..7e22dca7f 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -25,6 +25,20 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
+inline int32_t to_big_endian(int32_t i32) {
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#ifdef _WIN32
+ return _byteswap_ulong(i32);
+#else
+ return __builtin_bswap32(i32);
+#endif
+#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ return i32;
+#else
+#error "Unknown endianness"
+#endif
+}
+
void aiger_encode(std::ostream &f, int x)
{
log_assert(x >= 0);
@@ -684,12 +698,7 @@ struct XAigerWriter
if (!box_list.empty() || !ff_bits.empty()) {
auto write_buffer = [](std::stringstream &buffer, int i32) {
- // TODO: Don't assume we're on little endian
-#ifdef _WIN32
- int32_t i32_be = _byteswap_ulong(i32);
-#else
- int32_t i32_be = __builtin_bswap32(i32);
-#endif
+ int32_t i32_be = to_big_endian(i32);
buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
};
@@ -773,12 +782,7 @@ struct XAigerWriter
f << "h";
std::string buffer_str = h_buffer.str();
- // TODO: Don't assume we're on little endian
-#ifdef _WIN32
- int buffer_size_be = _byteswap_ulong(buffer_str.size());
-#else
- int buffer_size_be = __builtin_bswap32(buffer_str.size());
-#endif
+ int32_t buffer_size_be = to_big_endian(buffer_str.size());
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
f.write(buffer_str.data(), buffer_str.size());
@@ -787,18 +791,13 @@ struct XAigerWriter
auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
log_debug("flopNum = %zu\n", ff_bits.size());
write_r_buffer(ff_bits.size());
- int mergeability_class = 1;
- for (auto cell : ff_bits)
- write_r_buffer(mergeability_class++);
+ //int mergeability_class = 1;
+ //for (auto cell : ff_bits)
+ // write_r_buffer(mergeability_class++);
f << "r";
std::string buffer_str = r_buffer.str();
- // TODO: Don't assume we're on little endian
-#ifdef _WIN32
- int buffer_size_be = _byteswap_ulong(buffer_str.size());
-#else
- int buffer_size_be = __builtin_bswap32(buffer_str.size());
-#endif
+ int32_t buffer_size_be = to_big_endian(buffer_str.size());
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
f.write(buffer_str.data(), buffer_str.size());
}
@@ -831,12 +830,7 @@ struct XAigerWriter
f << "a";
std::string buffer_str = a_buffer.str();
- // TODO: Don't assume we're on little endian
-#ifdef _WIN32
- int buffer_size_be = _byteswap_ulong(buffer_str.size());
-#else
- int buffer_size_be = __builtin_bswap32(buffer_str.size());
-#endif
+ int32_t buffer_size_be = to_big_endian(buffer_str.size());
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
f.write(buffer_str.data(), buffer_str.size());
holes_module->design->remove(holes_module);
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 4ce76daa5..7d156fe03 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -35,6 +35,20 @@
YOSYS_NAMESPACE_BEGIN
+inline int32_t from_big_endian(int32_t i32) {
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#ifdef _WIN32
+ return _byteswap_ulong(i32);
+#else
+ return __builtin_bswap32(i32);
+#endif
+#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ return i32;
+#else
+#error "Unknown endianness"
+#endif
+}
+
struct ConstEvalAig
{
RTLIL::Module *module;
@@ -278,19 +292,14 @@ static uint32_t parse_xaiger_literal(std::istream &f)
f.read(reinterpret_cast<char*>(&l), sizeof(l));
if (f.gcount() != sizeof(l))
log_error("Offset %" PRId64 ": unable to read literal!\n", static_cast<int64_t>(f.tellg()));
- // TODO: Don't assume we're on little endian
-#ifdef _WIN32
- return _byteswap_ulong(l);
-#else
- return __builtin_bswap32(l);
-#endif
+ return from_big_endian(l);
}
static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal)
{
const unsigned variable = literal >> 1;
const bool invert = literal & 1;
- RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
+ RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : ""));
RTLIL::Wire *wire = module->wire(wire_name);
if (wire) return wire;
log_debug("Creating %s\n", wire_name.c_str());
@@ -309,7 +318,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
}
log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
- module->addNotGate(stringf("\\__%d__$not", variable), wire_inv, wire); // FIXME: is "$not" the right suffix?
+ module->addNotGate(stringf("\\__%d__$not", variable), wire_inv, wire);
return wire;
}
@@ -355,7 +364,8 @@ void AigerReader::parse_xaiger()
auto it = m->attributes.find("\\abc_box_id");
if (it == m->attributes.end())
continue;
- if (m->name[0] == '$') continue;
+ if (m->name.begins_with("$paramod"))
+ continue;
auto r = box_lookup.insert(std::make_pair(it->second.as_int(), m->name));
log_assert(r.second);
}
@@ -495,7 +505,7 @@ void AigerReader::parse_aiger_ascii()
if (!(f >> l1 >> l2))
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
log_debug("%d %d is a latch\n", l1, l2);
- log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
+ log_assert(!(l1 & 1));
RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index d3ad57d72..f4fcf5dcf 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -276,6 +276,12 @@ namespace RTLIL
return std::string(c_str() + pos, len);
}
+ bool begins_with(const char* prefix) const {
+ size_t len = strlen(prefix);
+ if (size() < len) return false;
+ return substr(0, len) == prefix;
+ }
+
bool ends_with(const char* suffix) const {
size_t len = strlen(suffix);
if (size() < len) return false;
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 99083c20a..04e7d5d13 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -61,17 +61,12 @@ extern "C" int Abc_RealMain(int argc, char *argv[]);
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-bool map_mux4;
-bool map_mux8;
-bool map_mux16;
-
bool markgroups;
int map_autoidx;
SigMap assign_map;
RTLIL::Module *module;
std::map<RTLIL::SigBit, int> signal_map;
std::map<RTLIL::SigBit, RTLIL::State> signal_init;
-pool<std::string> enabled_gates;
bool recover_init;
bool clk_polarity, en_polarity;
@@ -848,11 +843,6 @@ struct Abc9Pass : public Pass {
show_tempdir = true;
#endif
- map_mux4 = false;
- map_mux8 = false;
- map_mux16 = false;
- enabled_gates.clear();
-
#ifdef _WIN32
#ifndef ABCEXTERNAL
if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-09 07:19:14 +0000