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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 15:45:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 15:45:46 -0700 |
| commit | 342fc0a600584ab59fd24b6a6e22d49ff024c8d0 (patch) | |
| tree | b385743be7371078fb3b22d02ac3f63c052e5a92 | |
| parent | fb2758aade4561d8c379e8b9d97ee871b1bbfde3 (diff) | |
| download | yosys-342fc0a600584ab59fd24b6a6e22d49ff024c8d0.tar.gz yosys-342fc0a600584ab59fd24b6a6e22d49ff024c8d0.tar.bz2 yosys-342fc0a600584ab59fd24b6a6e22d49ff024c8d0.zip | |
parse_xaiger to cope with inouts
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 0afdf9592..72b37d21d 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -696,10 +696,6 @@ void AigerReader::post_process() RTLIL::Wire* wire = outputs[variable + co_count]; log_assert(wire); log_assert(wire->port_output); - if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) { - wire->port_output = false; - continue; - } if (index == 0) { // Cope with the fact that a CO might be identical @@ -797,8 +793,6 @@ void AigerReader::post_process() port_output = port_output || other_wire->port_output; } } - if ((port_input && port_output) || (!port_input && !port_output)) - continue; wire = module->addWire(name, width); wire->port_input = port_input; |