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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-13 08:24:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-13 08:24:33 -0700 |
| commit | 2052806d3361dca8a866aee0665af223db51bdbd (patch) | |
| tree | 20a0bf2f298bc641177612bbecf22c875b3431dd | |
| parent | 9d34cea65af5b34ce0930fb892fca6742db898ab (diff) | |
| download | yosys-2052806d3361dca8a866aee0665af223db51bdbd.tar.gz yosys-2052806d3361dca8a866aee0665af223db51bdbd.tar.bz2 yosys-2052806d3361dca8a866aee0665af223db51bdbd.zip | |
Fix LP SB_LUT4 timing
| -rw-r--r-- | techlibs/ice40/abc_lp.box | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box index dbc98d0c4..eb1cd0937 100644 --- a/techlibs/ice40/abc_lp.box +++ b/techlibs/ice40/abc_lp.box @@ -110,4 +110,4 @@ SB_CARRY 21 1 3 1 # Inputs: I0 I1 I2 I3 # Outputs: O SB_LUT4 22 1 4 1 -465 558 589 661 +661 589 558 465 |