iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Updated minisat	Clifford Wolf	2014-07-21	20	-45/+45
*	Using relative path names in minisat headers	Clifford Wolf	2014-07-21	1	-1/+1
*	Added yet another resource sharing test case	Clifford Wolf	2014-07-20	2	-0/+49
*	Added support for resource sharing in mux control logic	Clifford Wolf	2014-07-20	1	-86/+155
*	Added "select -assert-count"	Clifford Wolf	2014-07-20	1	-6/+43
*	Supercell creation for $div/$mod worked all along, fixed test benches	Clifford Wolf	2014-07-20	3	-8/+3
*	Improved tests/share/generate.py	Clifford Wolf	2014-07-20	1	-2/+12
*	Fixed creation of shift supercells in "share" pass	Clifford Wolf	2014-07-20	1	-4/+20
*	Small fix in tests/vloghtb/run-test.sh	Clifford Wolf	2014-07-20	1	-0/+2
*	Activated tests/share in "make test"	Clifford Wolf	2014-07-20	1	-0/+1
*	Added "miter -equiv -flatten"	Clifford Wolf	2014-07-20	2	-2/+15
*	Added call_on_selection() and call_on_module() API	Clifford Wolf	2014-07-20	4	-16/+37
*	Added tests/vloghtb/test_share.sh	Clifford Wolf	2014-07-20	5	-1/+57
*	Added tests/share for testing "share" supercell creation	Clifford Wolf	2014-07-20	3	-0/+58
*	Added "share" supercell creation	Clifford Wolf	2014-07-20	1	-1/+115
*	Added removing of always inactive cells to "share" pass	Clifford Wolf	2014-07-20	1	-8/+42
*	Progress in "share" pass	Clifford Wolf	2014-07-20	1	-112/+185
*	Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion	Clifford Wolf	2014-07-20	2	-3/+11
*	Added SIZE() macro	Clifford Wolf	2014-07-20	1	-0/+2
*	Added log_cell()	Clifford Wolf	2014-07-20	2	-0/+17
*	Progress in "share" pass	Clifford Wolf	2014-07-20	1	-19/+56
*	Added tests/vloghtb	Clifford Wolf	2014-07-20	2	-0/+18
*	Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...	Clifford Wolf	2014-07-20	1	-17/+21
*	Added support for $bu0 to verilog backend	Clifford Wolf	2014-07-20	1	-0/+16
*	Started to implement real resource sharing	Clifford Wolf	2014-07-19	2	-0/+444
*	Fixed log_id() memory corruption	Clifford Wolf	2014-07-19	2	-5/+10
*	Improved memory_share log messages	Clifford Wolf	2014-07-19	1	-3/+3
*	More verbose memory_share help message	Clifford Wolf	2014-07-19	1	-0/+17
*	Added SAT-based write-port sharing to memory_share	Clifford Wolf	2014-07-19	2	-0/+205
*	Added ModWalker helper class	Clifford Wolf	2014-07-19	1	-0/+298
*	Some "const" cleanups in SigMap	Clifford Wolf	2014-07-19	1	-4/+4
*	Fixed bug in memory_share feedback-to-en code	Clifford Wolf	2014-07-19	2	-4/+36
*	Added translation from read-feedback to en-signals in memory_share	Clifford Wolf	2014-07-18	3	-10/+264
*	Improved seeding of color rng in show command	Clifford Wolf	2014-07-18	1	-1/+3
*	Only create collision detect logic in memory_share if necessary	Clifford Wolf	2014-07-18	1	-4/+47
*	Bugfix in tests/memories/run-test.sh	Clifford Wolf	2014-07-18	1	-2/+2
*	added tests/memories	Clifford Wolf	2014-07-18	5	-0/+133
*	Added memory_share	Clifford Wolf	2014-07-18	3	-0/+266
*	Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>	Clifford Wolf	2014-07-18	1	-0/+1
*	Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port	Clifford Wolf	2014-07-18	1	-0/+15
*	Added function-like cell creation helpers	Clifford Wolf	2014-07-18	2	-73/+158
*	Added log_id() helper function	Clifford Wolf	2014-07-18	1	-0/+8
*	Also simulate unmapped memories in "make test"	Clifford Wolf	2014-07-17	1	-1/+1
*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17	2	-3/+66
*	Fixed simlib.v model for $mem	Clifford Wolf	2014-07-17	1	-15/+15
*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17	2	-0/+30
*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17	2	-9/+56
*	Improved opt_reduce handling of mem wr_en mux bits	Clifford Wolf	2014-07-17	1	-5/+18
*	Fixed RTLIL::SigSpec::append_bit() for appending constants	Clifford Wolf	2014-07-17	1	-2/+3
*	Added support for "blackbox" attribute to iopadmap	Clifford Wolf	2014-07-17	1	-1/+1