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author | Clifford Wolf <clifford@clifford.at> | 2014-07-19 15:34:14 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-19 15:34:14 +0200 |
commit | e0a819dbe507c90e201279db317c2251b3c691eb (patch) | |
tree | c7b39e0afaa7816163b8839f4c94a70b40f08668 | |
parent | 297a0962ea399fcfa80656af2bc887c5725f5b82 (diff) | |
download | yosys-e0a819dbe507c90e201279db317c2251b3c691eb.tar.gz yosys-e0a819dbe507c90e201279db317c2251b3c691eb.tar.bz2 yosys-e0a819dbe507c90e201279db317c2251b3c691eb.zip |
More verbose memory_share help message
-rw-r--r-- | passes/memory/memory_share.cc | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 20ff16dea..cde5f2183 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -708,6 +708,23 @@ struct MemorySharePass : public Pass { log("\n"); log("This pass merges share-able memory ports into single memory ports.\n"); log("\n"); + log("The following methods are used to consolidate the number of memory ports:\n"); + log("\n"); + log(" - When write ports are connected to async read ports accessing the same\n"); + log(" address, then this feedback path is converted to a write port with\n"); + log(" byte/part enable signals.\n"); + log("\n"); + log(" - When multiple write ports access the same adress then this is converted\n"); + log(" to a single write port with a more complex data and/or enable logic path.\n"); + log("\n"); + log(" - When multiple write ports are never accessed at the same time (a SAT\n"); + log(" solver is used to determine this), then the ports are merged into a single\n"); + log(" write port.\n"); + log("\n"); + log("Note that in addition to the algorithms implemented in this pass, the $memrd\n"); + log("and $memwr cells are also subject to generic resource sharing passes (and other\n"); + log("optimizations) such as opt_share.\n"); + log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); |