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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-17 12:10:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-17 12:10:57 +0200 |
| commit | 274c51487937e3ca37c3520e98e996cb5918e982 (patch) | |
| tree | 1ad5ccabcc35b0729a133c91969de111f6fa5e2b | |
| parent | b76bf05cda789219069c623d3f77cbc47c1eb57d (diff) | |
| download | yosys-274c51487937e3ca37c3520e98e996cb5918e982.tar.gz yosys-274c51487937e3ca37c3520e98e996cb5918e982.tar.bz2 yosys-274c51487937e3ca37c3520e98e996cb5918e982.zip | |
Fixed RTLIL::SigSpec::append_bit() for appending constants
| -rw-r--r-- | kernel/rtlil.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index c4c08d5b8..c232dadd2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1716,9 +1716,10 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) chunks.push_back(bit); else if (bit.wire == NULL) - if (chunks.back().wire == NULL) + if (chunks.back().wire == NULL) { chunks.back().data.bits.push_back(bit.data); - else + chunks.back().width++; + } else chunks.push_back(bit); else if (chunks.back().wire == bit.wire && chunks.back().offset + chunks.back().width == bit.offset) |