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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-20 15:23:08 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-20 15:33:07 +0200 |
| commit | 4c38ec1cc81c95b79fbd717dafd9f79708c123e8 (patch) | |
| tree | 21a1d1a3f5c1546e2942ea653a617747da0b6457 | |
| parent | 8d04ca7d22e375fbe075dee1f189669046ee8906 (diff) | |
| download | yosys-4c38ec1cc81c95b79fbd717dafd9f79708c123e8.tar.gz yosys-4c38ec1cc81c95b79fbd717dafd9f79708c123e8.tar.bz2 yosys-4c38ec1cc81c95b79fbd717dafd9f79708c123e8.zip | |
Added "miter -equiv -flatten"
| -rw-r--r-- | passes/sat/miter.cc | 14 | ||||
| -rw-r--r-- | tests/share/generate.py | 3 |
2 files changed, 15 insertions, 2 deletions
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 6c8e2ff48..0ef9e9aaa 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -27,6 +27,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, bool flag_make_outputs = false; bool flag_make_outcmp = false; bool flag_make_assert = false; + bool flag_flatten = false; log_header("Executing MITER pass (creating miter circuit).\n"); @@ -49,6 +50,10 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, flag_make_assert = true; continue; } + if (args[argidx] == "-flatten") { + flag_flatten = true; + continue; + } break; } if (argidx+3 != args.size() || args[argidx].substr(0, 1) == "-") @@ -287,6 +292,12 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, miter_module->add(not_cell); miter_module->fixup_ports(); + + if (flag_flatten) { + log_push(); + Pass::call_on_module(design, miter_module, "flatten; opt_const -undriven;;"); + log_pop(); + } } struct MiterPass : public Pass { @@ -317,6 +328,9 @@ struct MiterPass : public Pass { log(" -make_assert\n"); log(" also create an 'assert' cell that checks if trigger is always low.\n"); log("\n"); + log(" -flatten\n"); + log(" call 'flatten; opt_const -undriven;;' on the miter circuit.\n"); + log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { diff --git a/tests/share/generate.py b/tests/share/generate.py index 86be6b5ed..07821b721 100644 --- a/tests/share/generate.py +++ b/tests/share/generate.py @@ -35,7 +35,6 @@ for idx in range(100): print('copy uut_%05d gold' % idx) print('rename uut_%05d gate' % idx) print('share -aggressive gate') - print('miter -equiv -ignore_gold_x -make_outputs -make_outcmp gold gate miter') - print('flatten miter') + print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') print('sat -verify -prove trigger 0 -show-inputs -show-outputs miter') |