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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-18 11:36:34 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-18 11:36:34 +0200 |
| commit | a721f7d768feb3ce68cb384805ea7f1fde3e08ed (patch) | |
| tree | d14d6ecf2dbecb465d3795a7392984b65daa6391 | |
| parent | 309ae98246cf9ff115b7d95ae14991faf72a5a38 (diff) | |
| download | yosys-a721f7d768feb3ce68cb384805ea7f1fde3e08ed.tar.gz yosys-a721f7d768feb3ce68cb384805ea7f1fde3e08ed.tar.bz2 yosys-a721f7d768feb3ce68cb384805ea7f1fde3e08ed.zip | |
Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 17406d5d6..3a22d1371 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -542,6 +542,7 @@ struct RTLIL::SigSpec { static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + operator std::vector<RTLIL::SigBit>() const { return to_sigbit_vector(); } }; inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { |