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Age
Files
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*
Fix typo in passes/pmgen/README.md
Clifford Wolf
2019-02-21
1
-1
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+1
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Bugfix in ice40_dsp
Clifford Wolf
2019-02-21
3
-22
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+35
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Add ice40 test_dsp_map test case generator
Clifford Wolf
2019-02-20
2
-0
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+99
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Add "synth_ice40 -dsp"
Clifford Wolf
2019-02-20
2
-7
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+31
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Add FF support to wreduce
Clifford Wolf
2019-02-20
2
-1
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+73
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Improve iCE40 SB_MAC16 model
Clifford Wolf
2019-02-20
5
-121
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+179
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Detect and reject cases that do not map well to iCE40 DSPs (yet)
Clifford Wolf
2019-02-20
2
-2
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+17
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Add first draft of functional SB_MAC16 model
Clifford Wolf
2019-02-19
4
-53
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+467
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Add actual DSP inference to ice40_dsp pass
Clifford Wolf
2019-02-17
3
-24
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+214
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Merge branch 'master' of github.com:YosysHQ/yosys into pmgen
Clifford Wolf
2019-02-17
28
-199
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+627
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Merge pull request #811 from ucb-bar/firrtlfixes
Clifford Wolf
2019-02-17
6
-56
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+298
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Removed unused variables, functions.
Jim Lawson
2019-02-15
1
-20
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+0
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Append (instead of over-writing) EXTRA_FLAGS
Jim Lawson
2019-02-15
1
-1
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+1
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Update cells supported for verilog to FIRRTL conversion.
Jim Lawson
2019-02-15
5
-55
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+317
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Fix sign handling of real constants
Clifford Wolf
2019-02-13
1
-5
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+4
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Merge pull request #802 from whitequark/write_verilog_async_mem_ports
Clifford Wolf
2019-02-12
1
-38
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+41
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write_verilog: correctly emit asynchronous transparent ports.
whitequark
2019-01-29
1
-38
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+41
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Merge pull request #806 from daveshah1/fsm_opt_no_reset
Clifford Wolf
2019-02-12
1
-1
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+2
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fsm_opt: Fix runtime error for FSMs without a reset state
David Shah
2019-02-07
1
-1
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+2
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Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::...
Clifford Wolf
2019-02-06
1
-1
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+1
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Merge pull request #798 from mmicko/master
Clifford Wolf
2019-01-27
1
-1
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+1
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Fixed Anlogic simulation model
Miodrag Milanovic
2019-01-25
1
-1
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+1
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Merge pull request #800 from whitequark/write_verilog_tribuf
Clifford Wolf
2019-01-27
1
-0
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+12
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write_verilog: write $tribuf cell as ternary.
whitequark
2019-01-27
1
-0
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+12
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Merge branch 'whitequark-write_verilog_keyword'
Clifford Wolf
2019-01-27
5
-69
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+27
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Remove asicworld tests for (unsupported) switch-level modelling
Clifford Wolf
2019-01-27
4
-69
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+0
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write_verilog: escape names that match SystemVerilog keywords.
whitequark
2019-01-27
1
-0
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+27
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Merge pull request #796 from whitequark/proc_clean_typo
David Shah
2019-01-25
1
-1
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+1
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proc_clean: fix critical typo.
whitequark
2019-01-23
1
-1
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+1
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Merge pull request #793 from whitequark/proc_clean_fix_fully_def
Clifford Wolf
2019-01-19
1
-1
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+7
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proc_clean: fix fully def check to consider compare/signal length.
whitequark
2019-01-18
1
-1
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+7
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Cleanups in igloo2 example design
Clifford Wolf
2019-01-17
6
-7
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+4
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Add SF2 IO buffer insertion
Clifford Wolf
2019-01-17
6
-3
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+171
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Improve Igloo2 example
Clifford Wolf
2019-01-17
8
-22
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+41
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Add "synth_sf2 -vlog", fix "synth_sf2 -edif"
Clifford Wolf
2019-01-17
1
-2
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+17
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Add "write_edif -gndvccy"
Clifford Wolf
2019-01-17
1
-5
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+13
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Progress in pmgen
Clifford Wolf
2019-01-15
1
-3
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+11
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Progress in pmgen, add pmgen README
Clifford Wolf
2019-01-15
3
-14
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+260
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Fix pmgen "reject" statement
Clifford Wolf
2019-01-15
1
-1
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+1
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Progress in pmgen
Clifford Wolf
2019-01-15
3
-36
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+139
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Progress in pmgen
Clifford Wolf
2019-01-15
3
-21
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+157
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Progress in pmgen
Clifford Wolf
2019-01-15
5
-8
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+347
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Add mockup .pmg (pattern matcher generator) file
Clifford Wolf
2019-01-15
1
-0
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+75
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Add optional nullstr argument to log_id()
Clifford Wolf
2019-01-15
1
-1
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+3
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Fix handling of $shiftx in Verilog back-end
Clifford Wolf
2019-01-15
1
-3
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+6
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Merge pull request #788 from whitequark/master
Clifford Wolf
2019-01-15
1
-5
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+17
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manual: document some gates.
whitequark
2019-01-14
1
-9
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+11
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manual: explain $tribuf cell.
whitequark
2019-01-14
1
-0
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+10
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Merge pull request #787 from whitequark/flowmap_relax
Clifford Wolf
2019-01-15
7
-35
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+776
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flowmap: clean up terminology.
whitequark
2019-01-08
1
-17
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+18
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