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* Fix typo in passes/pmgen/README.mdClifford Wolf2019-02-211-1/+1
* Bugfix in ice40_dspClifford Wolf2019-02-213-22/+35
* Add ice40 test_dsp_map test case generatorClifford Wolf2019-02-202-0/+99
* Add "synth_ice40 -dsp"Clifford Wolf2019-02-202-7/+31
* Add FF support to wreduceClifford Wolf2019-02-202-1/+73
* Improve iCE40 SB_MAC16 modelClifford Wolf2019-02-205-121/+179
* Detect and reject cases that do not map well to iCE40 DSPs (yet)Clifford Wolf2019-02-202-2/+17
* Add first draft of functional SB_MAC16 modelClifford Wolf2019-02-194-53/+467
* Add actual DSP inference to ice40_dsp passClifford Wolf2019-02-173-24/+214
* Merge branch 'master' of github.com:YosysHQ/yosys into pmgenClifford Wolf2019-02-1728-199/+627
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| * Merge pull request #811 from ucb-bar/firrtlfixesClifford Wolf2019-02-176-56/+298
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| | * Removed unused variables, functions.Jim Lawson2019-02-151-20/+0
| | * Append (instead of over-writing) EXTRA_FLAGSJim Lawson2019-02-151-1/+1
| | * Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-155-55/+317
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| * Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| * Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
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| | * write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
| * | Merge pull request #806 from daveshah1/fsm_opt_no_resetClifford Wolf2019-02-121-1/+2
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| | * | fsm_opt: Fix runtime error for FSMs without a reset stateDavid Shah2019-02-071-1/+2
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| * / Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::...Clifford Wolf2019-02-061-1/+1
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| * Merge pull request #798 from mmicko/masterClifford Wolf2019-01-271-1/+1
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| | * Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
| * | Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
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| | * | write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
| * | | Merge branch 'whitequark-write_verilog_keyword'Clifford Wolf2019-01-275-69/+27
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| | * | Remove asicworld tests for (unsupported) switch-level modellingClifford Wolf2019-01-274-69/+0
| | * | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
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| * | Merge pull request #796 from whitequark/proc_clean_typoDavid Shah2019-01-251-1/+1
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| | * proc_clean: fix critical typo.whitequark2019-01-231-1/+1
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| * Merge pull request #793 from whitequark/proc_clean_fix_fully_defClifford Wolf2019-01-191-1/+7
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| | * proc_clean: fix fully def check to consider compare/signal length.whitequark2019-01-181-1/+7
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| * Cleanups in igloo2 example designClifford Wolf2019-01-176-7/+4
| * Add SF2 IO buffer insertionClifford Wolf2019-01-176-3/+171
| * Improve Igloo2 exampleClifford Wolf2019-01-178-22/+41
| * Add "synth_sf2 -vlog", fix "synth_sf2 -edif"Clifford Wolf2019-01-171-2/+17
| * Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
* | Progress in pmgenClifford Wolf2019-01-151-3/+11
* | Progress in pmgen, add pmgen READMEClifford Wolf2019-01-153-14/+260
* | Fix pmgen "reject" statementClifford Wolf2019-01-151-1/+1
* | Progress in pmgenClifford Wolf2019-01-153-36/+139
* | Progress in pmgenClifford Wolf2019-01-153-21/+157
* | Progress in pmgenClifford Wolf2019-01-155-8/+347
* | Add mockup .pmg (pattern matcher generator) fileClifford Wolf2019-01-151-0/+75
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* Add optional nullstr argument to log_id()Clifford Wolf2019-01-151-1/+3
* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
* Merge pull request #788 from whitequark/masterClifford Wolf2019-01-151-5/+17
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| * manual: document some gates.whitequark2019-01-141-9/+11
| * manual: explain $tribuf cell.whitequark2019-01-141-0/+10
* | Merge pull request #787 from whitequark/flowmap_relaxClifford Wolf2019-01-157-35/+776
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| * flowmap: clean up terminology.whitequark2019-01-081-17/+18