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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-27 09:25:18 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-27 09:25:18 +0100 |
| commit | 266511b29eb66486bd17210eb28454a2efee218a (patch) | |
| tree | d80f3496ea2d2d013d2d5334cb1e10b8d61653f4 | |
| parent | 81581f24fc88ec67093c330d145bb52badead85d (diff) | |
| parent | 0de328da8ffea4902c52b286d7b38d67a714c742 (diff) | |
| download | yosys-266511b29eb66486bd17210eb28454a2efee218a.tar.gz yosys-266511b29eb66486bd17210eb28454a2efee218a.tar.bz2 yosys-266511b29eb66486bd17210eb28454a2efee218a.zip | |
Merge pull request #798 from mmicko/master
Fixed Anlogic simulation model
| -rw-r--r-- | techlibs/anlogic/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v index 60a367928..058e76605 100644 --- a/techlibs/anlogic/cells_sim.v +++ b/techlibs/anlogic/cells_sim.v @@ -17,7 +17,7 @@ module AL_MAP_LUT1 ( ); parameter [1:0] INIT = 2'h0; parameter EQN = "(A)"; - assign Y = INIT >> A; + assign o = INIT >> a; endmodule module AL_MAP_LUT2 ( |