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| author | whitequark <whitequark@whitequark.org> | 2019-01-27 00:21:31 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-01-27 00:24:06 +0000 |
| commit | 3d7925ad9f7840d5269b84d053ae808f36ccf762 (patch) | |
| tree | c981d245e7999b1f3c034cb07de1267d2d5ce8e6 | |
| parent | c82aa49d9efa81c1e6c6e2d1a7507e3155d279e3 (diff) | |
| download | yosys-3d7925ad9f7840d5269b84d053ae808f36ccf762.tar.gz yosys-3d7925ad9f7840d5269b84d053ae808f36ccf762.tar.bz2 yosys-3d7925ad9f7840d5269b84d053ae808f36ccf762.zip | |
write_verilog: write $tribuf cell as ternary.
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 8da3c0627..54281e32e 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -789,6 +789,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$tribuf") + { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + f << stringf(" = "); + dump_sigspec(f, cell->getPort("\\EN")); + f << stringf(" ? "); + dump_sigspec(f, cell->getPort("\\A")); + f << stringf(" : %d'bz;\n", cell->parameters.at("\\WIDTH").as_int()); + return true; + } + if (cell->type == "$slice") { f << stringf("%s" "assign ", indent.c_str()); |