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authorClifford Wolf <clifford@clifford.at>2019-02-20 11:18:19 +0100
committerClifford Wolf <clifford@clifford.at>2019-02-20 11:18:19 +0100
commitdca65d83a0037539464d303ea8751a3e06a92e03 (patch)
tree6609dce7db4f254131e7e0cefa1aefa5e7c9d64d
parent62493c91b24c1775f82e64712bf42b175944fe08 (diff)
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Detect and reject cases that do not map well to iCE40 DSPs (yet)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
-rw-r--r--passes/pmgen/ice40_dsp.cc9
-rw-r--r--passes/pmgen/ice40_dsp.pmg10
2 files changed, 17 insertions, 2 deletions
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 7463d598f..8c50a9393 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -59,10 +59,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
return;
}
- log(" replacing $mul with SB_MAC16 cell.\n");
-
bool mul_signed = pm.st.mul->getParam("\\A_SIGNED").as_bool();
+ if (mul_signed) {
+ log(" inference of signed iCE40 DSP arithmetic is currently not supported.\n");
+ return;
+ }
+
+ log(" replacing $mul with SB_MAC16 cell.\n");
+
Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
pm.module->swap_names(cell, pm.st.mul);
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 58e1ce0e0..96c62e313 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -100,6 +100,16 @@ code addAB sigS
addAB = addB;
sigS = port(addB, \A);
}
+ if (addAB) {
+ int natural_mul_width = GetSize(sigA) + GetSize(sigB);
+ int actual_mul_width = GetSize(sigY);
+ int actual_acc_width = GetSize(sigS);
+
+ if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
+ reject;
+ if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
+ reject;
+ }
endcode
match muxA