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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-15 10:55:27 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-01-15 10:55:27 +0100 |
| commit | 6c5049f016538e887476bb66d3f653155fa354ff (patch) | |
| tree | 591a28af00e484bd18ea0a0ad63bedf90a031950 | |
| parent | 1d82a88e948e614ada66b0fd59e9cc0aa569afae (diff) | |
| download | yosys-6c5049f016538e887476bb66d3f653155fa354ff.tar.gz yosys-6c5049f016538e887476bb66d3f653155fa354ff.tar.bz2 yosys-6c5049f016538e887476bb66d3f653155fa354ff.zip | |
Fix handling of $shiftx in Verilog back-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 2537e18e5..8da3c0627 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -709,11 +709,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$shiftx") { + std::string temp_id = next_auto_id(); + f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort("\\A"))-1, temp_id.c_str()); + dump_sigspec(f, cell->getPort("\\A")); + f << stringf(";\n"); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - f << stringf(" = "); - dump_sigspec(f, cell->getPort("\\A")); - f << stringf("["); + f << stringf(" = %s[", temp_id.c_str()); if (cell->getParam("\\B_SIGNED").as_bool()) f << stringf("$signed("); dump_sigspec(f, cell->getPort("\\B")); |