iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Added stackmap<> container	Clifford Wolf	2014-08-17	2	-2/+109
*	Renamed toposort.h to utils.h	Clifford Wolf	2014-08-17	3	-2/+2
*	Added module->uniquify()	Clifford Wolf	2014-08-16	5	-15/+29
*	Fixed AOI/OAI expr handling in verilog backend	Clifford Wolf	2014-08-16	1	-4/+4
*	Multiply using a carry-save accumulator	Clifford Wolf	2014-08-16	1	-5/+45
*	Added "test_cell -s <seed>"	Clifford Wolf	2014-08-16	1	-5/+17
*	AST ProcessGenerator: replaced subst__{from,to} with subst__map	Clifford Wolf	2014-08-16	1	-41/+26
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16	8	-48/+399
*	Added CellTypes::cell_evaluable()	Clifford Wolf	2014-08-16	1	-31/+37
*	Changes in techmap $__alu interface	Clifford Wolf	2014-08-16	1	-17/+17
*	Added "opt -fast"	Clifford Wolf	2014-08-16	1	-19/+45
*	Added log_spacer()	Clifford Wolf	2014-08-16	3	-2/+20
*	Bugfix in iopadmap	Clifford Wolf	2014-08-15	1	-1/+3
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15	6	-39/+38
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	19	-47/+47
*	Removed old doc references to $safe_pmux	Clifford Wolf	2014-08-15	2	-5/+1
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15	4	-10/+22
*	Added Frontend "+/" filename syntax for files from proc_share_dir	Clifford Wolf	2014-08-15	1	-1/+4
*	document "techmap -map %<design-name>"	Clifford Wolf	2014-08-15	1	-0/+3
*	Fixed bug in "read_verilog -ignore_redef"	Clifford Wolf	2014-08-15	1	-1/+1
*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14	3	-11/+20
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14	3	-21/+31
*	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	Clifford Wolf	2014-08-14	2	-25/+64
*	Fixed line numbers when using here-doc macros	Clifford Wolf	2014-08-14	1	-4/+9
*	Fixed handling of task outputs	Clifford Wolf	2014-08-14	1	-2/+4
*	Simplified $__arraymul techmap rule	Clifford Wolf	2014-08-14	1	-7/+13
*	Added module->ports	Clifford Wolf	2014-08-14	9	-10/+23
*	Refactoring of CellType class	Clifford Wolf	2014-08-14	3	-155/+139
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	16	-98/+21
*	Some improvements in FSM mapping and recoding	Clifford Wolf	2014-08-14	3	-9/+18
*	Added "abc -D" for setting delay target	Clifford Wolf	2014-08-14	1	-5/+18
*	Updated ABC to 4935c2b946de	Clifford Wolf	2014-08-14	1	-1/+1
*	Added techmap support for actual lookahead carry unit	Clifford Wolf	2014-08-13	1	-22/+73
*	Preparations for lookahead ALU support in techmap.v	Clifford Wolf	2014-08-13	1	-28/+92
*	Filter ANSI escape sequences from ABC output	Clifford Wolf	2014-08-13	1	-0/+15
*	New interface for $__alu in techmap.v	Clifford Wolf	2014-08-13	1	-129/+62
*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13	2	-1/+21
*	Fixed handling of constant-true branches in proc_clean	Clifford Wolf	2014-08-12	2	-2/+3
*	Added test_verific mode to tests/fsm/generate.py	Clifford Wolf	2014-08-12	1	-7/+17
*	Fixed SigBit(RTLIL::Wire *wire) constructor	Clifford Wolf	2014-08-12	1	-1/+1
*	Fixed building verific bindings	Clifford Wolf	2014-08-12	2	-3/+3
*	Added multi-dim memory test (requires iverilog git head)	Clifford Wolf	2014-08-12	1	-0/+11
*	Another build fix by americanrouter (via reddit)	Clifford Wolf	2014-08-11	1	-0/+3
*	Fixed FSM mapping for multiple reset-like signals	Clifford Wolf	2014-08-10	2	-8/+43
*	Fixed "share" for complex scenarios with never-active cells	Clifford Wolf	2014-08-09	1	-6/+22
*	Do not share any $reduce_* cells (its complicated and not worth it anyways)	Clifford Wolf	2014-08-09	1	-19/+0
*	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	Clifford Wolf	2014-08-09	3	-51/+103
*	Improved FSM tests	Clifford Wolf	2014-08-08	4	-2/+5
*	Another fsm_extract bugfix	Clifford Wolf	2014-08-08	1	-0/+4
*	Fixed "fsm -export"	Clifford Wolf	2014-08-08	2	-6/+5