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* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-314-9/+102
* Added design->scratchpadClifford Wolf2014-08-3010-64/+91
* Added $alu cell typeClifford Wolf2014-08-305-3/+67
* Added autotest -e (do not use -noexpr on write_verilog)Clifford Wolf2014-08-303-4/+6
* Improved write address decoder generation memory_mapClifford Wolf2014-08-301-16/+28
* Fixed module->addPmux()Clifford Wolf2014-08-301-1/+0
* Using worker class in memory_mapClifford Wolf2014-08-301-226/+231
* Replaced $__alu CO/CS outputs with full-width CO outputClifford Wolf2014-08-301-32/+28
* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-301-1/+6
* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-301-0/+10
* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-301-20/+75
* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-271-0/+5
* Fixed printing of multi-line Makefile.confClifford Wolf2014-08-271-1/+6
* Implemented "rename -enumerate -pattern"Clifford Wolf2014-08-261-4/+13
* Print Makefile.conf as make info messageClifford Wolf2014-08-261-1/+4
* Checking for valid CONFIG value in MakefileClifford Wolf2014-08-251-6/+6
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-241-0/+35
* Added some additional log messages to opt_constClifford Wolf2014-08-241-1/+10
* Added is_signed argument to SigSpec.as_int() and Const.as_int()Clifford Wolf2014-08-242-6/+9
* azonenberg: Make dump_vcd save model when temporal induction fails due to ste...Clifford Wolf2014-08-241-0/+2
* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-231-2/+1
* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-238-195/+21
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-2322-89/+116
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-2316-728/+713
* Added "stat -width"Clifford Wolf2014-08-221-4/+37
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-2211-14/+101
* Added DPI-C documentation to README fileClifford Wolf2014-08-221-0/+12
* Added support for non-standard <plugin>:<c_name> DPI syntaxClifford Wolf2014-08-221-0/+12
* Archibald Rust and Clifford Wolf: ffi-based dpi_call()Clifford Wolf2014-08-223-9/+93
* Added "plugin" commandClifford Wolf2014-08-226-10/+136
* Updated ABC to 4d547a5e065bClifford Wolf2014-08-221-1/+1
* Cosmetic changes to FSM testsClifford Wolf2014-08-211-1/+1
* Fixed small memory leak in ast simplifyClifford Wolf2014-08-211-3/+3
* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-213-9/+20
* Added AstNode::asInt()Clifford Wolf2014-08-213-2/+24
* Fixed memory leak in DPI function callsClifford Wolf2014-08-211-0/+4
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-08-212-63/+100
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| * Added mod->addGate() methods for new gate typesClifford Wolf2014-08-192-63/+100
* | Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-218-3/+135
* | Added support for global tasks and functionsClifford Wolf2014-08-213-27/+49
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* Using "via_celltype" in $mul carry-save-acc implementationClifford Wolf2014-08-181-34/+72
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-183-18/+110
* Performance fix for new $__lcu techmap ruleClifford Wolf2014-08-181-7/+5
* Replaced recursive lcu scheme with bk adderClifford Wolf2014-08-181-61/+31
* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-183-1/+41
* Fixed proc_{self,share}_dirname error handlingClifford Wolf2014-08-171-4/+2
* Makefile fixesClifford Wolf2014-08-171-1/+4
* Improved AST ProcessGenerator performanceClifford Wolf2014-08-171-3/+3
* Improved sig.remove2() performanceClifford Wolf2014-08-171-2/+11
* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-173-24/+22