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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-12 15:39:48 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-12 15:39:48 +0200 |
| commit | e5ac8fdf2bf9d4bed41daf420aa8a94018c0ded4 (patch) | |
| tree | b5e51348a3cf135dcbfea42d9c00523f8492356f | |
| parent | 593264e9edce8b1df1d5b691353fa592261d4f3b (diff) | |
| download | yosys-e5ac8fdf2bf9d4bed41daf420aa8a94018c0ded4.tar.gz yosys-e5ac8fdf2bf9d4bed41daf420aa8a94018c0ded4.tar.bz2 yosys-e5ac8fdf2bf9d4bed41daf420aa8a94018c0ded4.zip | |
Fixed SigBit(RTLIL::Wire *wire) constructor
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8ec599417..1e967f26c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -852,7 +852,7 @@ struct RTLIL::SigBit SigBit() : wire(NULL), data(RTLIL::State::S0) { } SigBit(RTLIL::State bit) : wire(NULL), data(bit) { } - SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0) { log_assert(wire && wire->width == 1); } + SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); } SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); } SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; } SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; } |