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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-14 11:22:45 +0200 | 
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-14 11:22:45 +0200 | 
| commit | 28cf48e31f049f8343023de46cd916ac47fcfc5d (patch) | |
| tree | a9f23f5705ab78e95a5f03cd55430942beae6862 | |
| parent | 996c06f64dcb1619584c88d101c5ba258b2b26af (diff) | |
| download | yosys-28cf48e31f049f8343023de46cd916ac47fcfc5d.tar.gz yosys-28cf48e31f049f8343023de46cd916ac47fcfc5d.tar.bz2 yosys-28cf48e31f049f8343023de46cd916ac47fcfc5d.zip | |
Some improvements in FSM mapping and recoding
| -rw-r--r-- | passes/fsm/fsm_map.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_recode.cc | 22 | ||||
| -rw-r--r-- | tests/fsm/generate.py | 3 | 
3 files changed, 18 insertions, 9 deletions
| diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 048cf7e5f..60580eb46 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -285,7 +285,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)  				}  			} -			RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux"); +			RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$pmux");  			mux_cell->setPort("\\A", sig_a);  			mux_cell->setPort("\\B", sig_b);  			mux_cell->setPort("\\S", sig_s); diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 40fed130e..9c0da0a37 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -53,10 +53,10 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs  	std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").decode_string() : "auto";  	log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str()); -	if (encoding != "none" && encoding != "one-hot" && encoding != "binary") { -		if (encoding != "auto") -			log("  unkown encoding `%s': using auto (%s) instead.\n", encoding.c_str(), default_encoding.c_str()); -		encoding = default_encoding; + +	if (encoding != "none" && encoding != "one-hot" && encoding != "binary" && encoding != "auto") { +		log("  unkown encoding `%s': using auto instead.\n", encoding.c_str()); +		encoding = "auto";  	}  	if (encoding == "none") { @@ -70,10 +70,18 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs  	if (fm_set_fsm_file != NULL)  		fm_set_fsm_print(cell, module, fsm_data, "r", fm_set_fsm_file); +	if (encoding == "auto") { +		if (!default_encoding.empty()) +			encoding = default_encoding; +		else +			encoding = SIZE(fsm_data.state_table) < 32 ? "one-hot" : "binary"; +		log("  mapping auto encoding to `%s` for this FSM.\n", encoding.c_str()); +	} +  	if (encoding == "one-hot") {  		fsm_data.state_bits = fsm_data.state_table.size();  	} else -	if (encoding == "auto" || encoding == "binary") { +	if (encoding == "binary") {  		fsm_data.state_bits = ceil(log2(fsm_data.state_table.size()));  	} else  		log_error("FSM encoding `%s' is not supported!\n", encoding.c_str()); @@ -88,7 +96,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs  			new_code = RTLIL::Const(RTLIL::State::Sa, fsm_data.state_bits);  			new_code.bits[state_idx] = RTLIL::State::S1;  		} else -		if (encoding == "auto" || encoding == "binary") { +		if (encoding == "binary") {  			new_code = RTLIL::Const(state_idx, fsm_data.state_bits);  		} else  			log_abort(); @@ -124,7 +132,7 @@ struct FsmRecodePass : public Pass {  	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)  	{  		FILE *fm_set_fsm_file = NULL; -		std::string default_encoding = "one-hot"; +		std::string default_encoding;  		log_header("Executing FSM_RECODE pass (re-assigning FSM state encoding).\n");  		size_t argidx; diff --git a/tests/fsm/generate.py b/tests/fsm/generate.py index 66ca2af5e..b5b4626df 100644 --- a/tests/fsm/generate.py +++ b/tests/fsm/generate.py @@ -52,7 +52,8 @@ for idx in range(50):          print('  output reg%s [%d:0] y;' % (random.choice(['', ' signed']), random.randint(0, 31)))          print('  output reg%s [%d:0] z;' % (random.choice(['', ' signed']), random.randint(0, 31)))          state_bits = random.randint(5, 16); -        print('  reg [%d:0] state;' % (state_bits-1)) +        print('  %sreg [%d:0] state;' % (random.choice(['', '(* fsm_encoding = "one-hot" *)', +                '(* fsm_encoding = "binary" *)']), state_bits-1))          states=[]          for i in range(random.randint(2, 10)):              n = random.randint(0, 2**state_bits-1) | 
