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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-13 13:03:38 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-13 13:03:38 +0200 |
| commit | f53984795d38946ee71684d88883cafd9f58f603 (patch) | |
| tree | 21aff3aeacec725c3f7ff1eea59561955e735e50 | |
| parent | 9d353fc543295db7d6f4b4ba60c2b66a509b3ee2 (diff) | |
| download | yosys-f53984795d38946ee71684d88883cafd9f58f603.tar.gz yosys-f53984795d38946ee71684d88883cafd9f58f603.tar.bz2 yosys-f53984795d38946ee71684d88883cafd9f58f603.zip | |
Added support for non-standard """ macro bodies
| -rw-r--r-- | README | 9 | ||||
| -rw-r--r-- | frontends/verilog/preproc.cc | 13 |
2 files changed, 21 insertions, 1 deletions
@@ -281,6 +281,15 @@ Verilog Attributes and non-standard features to simply declare a module port as 'input' or 'output' in the module body. +- When defining a macro with `define, all text between tripple double quotes + is interpreted as macro body, even if it contains unescaped newlines. The + tripple double quotes are removed from the macro body. For example: + + `define MY_MACRO(a, b) """ + assign a = 23; + assign b = 42; + """ + - Sized constants (the syntax <size>'s?[bodh]<value>) support constant expressions as <size>. If the expresion is not a simple identifier, it must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 8efd4d7c3..7935fbc34 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -131,6 +131,12 @@ static std::string next_token(bool pass_newline = false) token += ch; } } + if (token == "\"\"" && (ch = next_char()) != 0) { + if (ch == '"') + token += ch; + else + return_char(ch); + } } else if (ch == '/') { @@ -311,12 +317,17 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m std::map<std::string, int> args; skip_spaces(); name = next_token(true); + bool here_doc_mode = false; int newline_count = 0; int state = 0; if (skip_spaces() != "") state = 3; while (!tok.empty()) { tok = next_token(); + if (tok == "\"\"\"") { + here_doc_mode = !here_doc_mode; + continue; + } if (state == 0 && tok == "(") { state = 1; skip_spaces(); @@ -332,7 +343,7 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m } else { if (state != 2) state = 3; - if (tok == "\n") { + if (tok == "\n" && !here_doc_mode) { return_char('\n'); break; } |