aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* verilog_backend: Correctly sign extend output of signed `$modfloor`Jannis Harder2022-11-301-2/+2
* verilog_backend: Add -noparallelcase optionJannis Harder2022-11-301-7/+31
* simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signalJannis Harder2022-11-301-2/+8
* simlib: Silence iverilog warning for `$lut`Jannis Harder2022-11-301-1/+1
* simlib: Fix wide $bmux and avoid iverilog warningsJannis Harder2022-11-301-2/+2
* satgen, simlib: Consistent x-propagation for `$pmux` cellsJannis Harder2022-11-302-18/+20
* opt_expr: Fix shift/shiftx optimizationsJannis Harder2022-11-301-3/+3
* opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cellsJannis Harder2022-11-291-0/+33
* opt_expr: Optimize bitwise logic ops with one fully const inputJannis Harder2022-11-291-0/+81
* simplemap: Map `$xnor` to `$_XNOR_` cellsJannis Harder2022-11-293-20/+5
* Bump versiongithub-actions[bot]2022-11-291-1/+1
* Merge pull request #3565 from jix/sat-def-formalJannis Harder2022-11-283-10/+46
|\
| * sat: Add -set-def-formal option to force defined $any* outputsJannis Harder2022-11-283-10/+46
|/
* Bump versiongithub-actions[bot]2022-11-261-1/+1
* Merge pull request #3561 from YosysHQ/tcl_shellMiodrag Milanović2022-11-252-8/+34
|\
| * Add TCL interactive shell modeMiodrag Milanovic2022-11-252-8/+34
* | Merge pull request #3560 from YosysHQ/verific_confMiodrag Milanović2022-11-253-8/+43
|\ \ | |/ |/|
| * update documentationMiodrag Milanovic2022-11-251-3/+3
| * Support importing verilog configurations using VerificMiodrag Milanovic2022-11-253-5/+40
* | Bump versiongithub-actions[bot]2022-11-251-1/+1
* | Remove docs dependency on yosys repo (#3558)KrystalDelusion2022-11-2439-18/+905
|/
* Merge pull request #3552 from daglem/fix-sv-c-array-dimensionsJannis Harder2022-11-231-3/+3
|\
| * Correct interpretation of SystemVerilog C-style array dimensionsDag Lem2022-11-131-3/+3
* | Bump versiongithub-actions[bot]2022-11-221-1/+1
* | Merge branch 'zachjs-master'Jannis Harder2022-11-213-0/+52
|\ \
| * | verilog: Support module-scoped task/function callsZachary Snow2022-10-293-0/+52
* | | mention prerequisites in fsm_detect and fsm helpN. Engelhardt2022-11-212-0/+18
* | | Bump versiongithub-actions[bot]2022-11-181-1/+1
* | | fabulous: Allow adding extra custom prims and map rulesgatecat2022-11-174-0/+53
* | | fabulous: improvements to the passgatecat2022-11-1713-139/+340
* | | fabulous: Unify and update primitivesgatecat2022-11-173-852/+356
* | | Introduce RegFile mappingsTaoBi222022-11-174-2/+95
* | | Replace synth call with components, reintroduce flags and correct vpr flag im...TaoBi222022-11-171-4/+76
* | | Reorder operations to load in primitive library before hierarchy passTaoBi222022-11-171-5/+6
* | | Add plib flag to specify custom primitive library pathTaoBi222022-11-171-2/+14
* | | Remove flattening from FABulous passTaoBi222022-11-171-11/+2
* | | Remove ALL currently unused flags (some to be reintroduced later and passed t...TaoBi222022-11-171-82/+3
* | | Add synth_fabulous ScriptPassTaoBi222022-11-178-0/+1282
* | | Bump versiongithub-actions[bot]2022-11-171-1/+1
* | | Slowing down clock to have same metadataMiodrag Milanovic2022-11-161-2/+2
* | | Bump versiongithub-actions[bot]2022-11-161-1/+1
* | | faketime to make PDFs uniqueMiodrag Milanovic2022-11-151-2/+2
* | | Rst docs conversion (#3496)KrystalDelusion2022-11-1557-2/+7792
* | | Merge pull request #3547 from YosysHQ/update_abcMiodrag Milanović2022-11-141-1/+1
|\ \ \ | |_|/ |/| |
| * | Update ABCMiodrag Milanovic2022-11-091-1/+1
* | | Bump versiongithub-actions[bot]2022-11-101-1/+1
* | | Add missing memory width assert preventing division by zero (#3546)Emil J2022-11-091-0/+1
|/ /
* | Bump versiongithub-actions[bot]2022-11-091-1/+1
* | Next dev cycleMiodrag Milanovic2022-11-082-2/+5
* | Release version 0.23Miodrag Milanovic2022-11-082-3/+3
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 18:45:56 +0000