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| author | Jannis Harder <me@jix.one> | 2022-11-02 17:45:46 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-11-29 19:06:45 +0100 |
| commit | 661fa5ff92f19675cfd87754a99d0c5c42c9df13 (patch) | |
| tree | c045e5326f7b00ae22440c51703701ba26d36ed8 | |
| parent | f9db7c0599d87fa7d61b72979029c5894e3dbe6b (diff) | |
| download | yosys-661fa5ff92f19675cfd87754a99d0c5c42c9df13.tar.gz yosys-661fa5ff92f19675cfd87754a99d0c5c42c9df13.tar.bz2 yosys-661fa5ff92f19675cfd87754a99d0c5c42c9df13.zip | |
simplemap: Map `$xnor` to `$_XNOR_` cells
The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of
the `$_XNOR_` cell.
| -rw-r--r-- | passes/techmap/simplemap.cc | 16 | ||||
| -rw-r--r-- | tests/opt/opt_expr_xnor.ys | 2 | ||||
| -rw-r--r-- | tests/opt/opt_expr_xor.ys | 7 |
3 files changed, 5 insertions, 20 deletions
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index f75b82919..baae8c6af 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -61,25 +61,11 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool()); - if (cell->type == ID($xnor)) - { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y)); - - for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); - gate->setPort(ID::A, sig_t[i]); - gate->setPort(ID::Y, sig_y[i]); - } - - sig_y = sig_t; - } - IdString gate_type; if (cell->type == ID($and)) gate_type = ID($_AND_); if (cell->type == ID($or)) gate_type = ID($_OR_); if (cell->type == ID($xor)) gate_type = ID($_XOR_); - if (cell->type == ID($xnor)) gate_type = ID($_XOR_); + if (cell->type == ID($xnor)) gate_type = ID($_XNOR_); log_assert(!gate_type.empty()); for (int i = 0; i < GetSize(sig_y); i++) { diff --git a/tests/opt/opt_expr_xnor.ys b/tests/opt/opt_expr_xnor.ys index f8ef0d352..225df7076 100644 --- a/tests/opt/opt_expr_xnor.ys +++ b/tests/opt/opt_expr_xnor.ys @@ -32,7 +32,7 @@ select -assert-count 1 c:* cd fine_keepdc simplemap opt_expr -keepdc -select -assert-count 1 t:$_XOR_ +select -assert-count 1 t:$_XNOR_ cd miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3 diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys index 8874f2775..9edec35d6 100644 --- a/tests/opt/opt_expr_xor.ys +++ b/tests/opt/opt_expr_xor.ys @@ -22,9 +22,8 @@ simplemap equiv_opt -assert opt_expr design -load postopt select -assert-none t:$_XOR_ -select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_ -select -assert-count 3 t:$_NOT_ - +select -assert-none t:$_XNOR_ +select -assert-count 2 t:$_NOT_ design -reset read_verilog -icells <<EOT @@ -36,7 +35,7 @@ EOT select -assert-count 2 t:$_XNOR_ equiv_opt -assert opt_expr design -load postopt -select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_ +select -assert-none t:$_XNOR_ select -assert-count 1 t:$_NOT_ |