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| author | TaoBi22 <beahealy22@gmail.com> | 2022-09-27 17:46:52 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2022-11-17 13:34:58 +0100 |
| commit | df5617856781aca9a09a647f72817c076e5e55fe (patch) | |
| tree | c8188e641d34d9daa1f9fadcc5871669bc11e530 | |
| parent | da32f21b5908972430e687d805bb84635f2e9b43 (diff) | |
| download | yosys-df5617856781aca9a09a647f72817c076e5e55fe.tar.gz yosys-df5617856781aca9a09a647f72817c076e5e55fe.tar.bz2 yosys-df5617856781aca9a09a647f72817c076e5e55fe.zip | |
Reorder operations to load in primitive library before hierarchy pass
| -rw-r--r-- | techlibs/fabulous/synth_fabulous.cc | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 478569555..17c67a636 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -121,7 +121,7 @@ struct SynthPass : public ScriptPass if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); - log_header(design, "Executing SYNTH pass.\n"); + log_header(design, "Executing SYNTH_FABULOUS pass.\n"); log_push(); run_script(design, run_from, run_to); @@ -131,6 +131,11 @@ struct SynthPass : public ScriptPass void script() override { + if (plib.empty()) + run("read_verilog -lib +/fabulous/prims.v"); + else + run("read_verilog -lib " + plib); + if (top_module.empty()) { if (autotop) run("hierarchy -check -auto-top"); @@ -139,10 +144,6 @@ struct SynthPass : public ScriptPass } else run(stringf("hierarchy -check -top %s", top_module.c_str())); - if (plib.empty()) - run("read_verilog -lib +/fabulous/prims.v"); - else - run("read_verilog -lib " + plib); run("proc"); run("tribuf -logic"); run("deminout"); |