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author | Jannis Harder <me@jix.one> | 2022-11-21 17:46:34 +0100 |
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committer | Jannis Harder <me@jix.one> | 2022-11-21 17:47:43 +0100 |
commit | 239ecf9185e319b98d809d16d6f7d01dcb003b70 (patch) | |
tree | 63edeb211149b2567d5050a2c5bf5a79ed59e083 | |
parent | b64141f48bcd0d8283ddbe849ccf794c8b12d780 (diff) | |
parent | 71e7e09092dc262b7cddbfc99e1b92e81ac58f21 (diff) | |
download | yosys-239ecf9185e319b98d809d16d6f7d01dcb003b70.tar.gz yosys-239ecf9185e319b98d809d16d6f7d01dcb003b70.tar.bz2 yosys-239ecf9185e319b98d809d16d6f7d01dcb003b70.zip |
Merge branch 'zachjs-master'
-rw-r--r-- | CHANGELOG | 3 | ||||
-rw-r--r-- | frontends/ast/simplify.cc | 4 | ||||
-rw-r--r-- | tests/simple/module_scope_func.v | 45 |
3 files changed, 52 insertions, 0 deletions
@@ -5,6 +5,9 @@ List of major changes and improvements between releases Yosys 0.23 .. Yosys 0.23-dev -------------------------- + * Verilog + - Support for module-scoped identifiers referring to tasks and functions. + Yosys 0.22 .. Yosys 0.23 -------------------------- * New commands and options diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 49bf9af09..c932e2c49 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -3656,6 +3656,8 @@ skip_dynamic_range_lvalue_expansion:; goto apply_newNode; } + if (current_scope.count(str) == 0) + str = try_pop_module_prefix(); if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION) log_file_error(filename, location.first_line, "Can't resolve function name `%s'.\n", str.c_str()); } @@ -3727,6 +3729,8 @@ skip_dynamic_range_lvalue_expansion:; goto apply_newNode; } + if (current_scope.count(str) == 0) + str = try_pop_module_prefix(); if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK) log_file_error(filename, location.first_line, "Can't resolve task name `%s'.\n", str.c_str()); } diff --git a/tests/simple/module_scope_func.v b/tests/simple/module_scope_func.v new file mode 100644 index 000000000..928078da4 --- /dev/null +++ b/tests/simple/module_scope_func.v @@ -0,0 +1,45 @@ +// Some strict implementatins either forbid hierarchical identifiers within +// constant expressions, or forbid declaring functions in generate blocks, or +// both. Yosys and Iverilog are not strict in either of these ways. +module module_scope_func_top( + input wire inp, + output wire [31:0] out1, out2, out4, out5, out7, out8, + output reg [31:0] out3, out6, out9 +); + function automatic integer incr; + input integer value; + incr = value + 1; + endfunction + task send; + output integer out; + out = 55; + endtask + + assign out1 = module_scope_func_top.incr(inp); + localparam C = module_scope_func_top.incr(10); + assign out2 = C; + initial module_scope_func_top.send(out3); + + if (1) begin : blk + // shadows module_scope_func_top.incr + function automatic integer incr; + input integer value; + incr = value * 2; + endfunction + // shadows module_scope_func_top.send + task send; + output integer out; + out = 66; + endtask + + assign out4 = module_scope_func_top.incr(inp); + localparam D = module_scope_func_top.incr(20); + assign out5 = D; + initial module_scope_func_top.send(out6); + + assign out7 = incr(inp); + localparam E = incr(30); + assign out8 = E; + initial send(out9); + end +endmodule |