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authorJannis Harder <me@jix.one>2022-11-10 16:27:13 +0100
committerJannis Harder <me@jix.one>2022-11-30 18:24:35 +0100
commit82b630a246cd02a2df56786e7a25d4c38103e8cf (patch)
tree81fc93fc0d71989339f2e267d9ab8b83a47d1608
parent5cb7d0fe9d61ac0e07c697cc012e11aeffa806bc (diff)
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verilog_backend: Correctly sign extend output of signed `$modfloor`
-rw-r--r--backends/verilog/verilog_backend.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 38a89f6ac..5a9d9b63f 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1209,7 +1209,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($modfloor))
{
// wire truncated = $signed(A) % $signed(B);
- // assign Y = (A[-1] == B[-1]) || truncated == 0 ? truncated : $signed(B) + $signed(truncated);
+ // assign Y = (A[-1] == B[-1]) || truncated == 0 ? $signed(truncated) : $signed(B) + $signed(truncated);
if (cell->getParam(ID::A_SIGNED).as_bool() && cell->getParam(ID::B_SIGNED).as_bool()) {
SigSpec sig_a = cell->getPort(ID::A);
@@ -1229,7 +1229,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
dump_sigspec(f, sig_a.extract(sig_a.size()-1));
f << stringf(" == ");
dump_sigspec(f, sig_b.extract(sig_b.size()-1));
- f << stringf(") || %s == 0 ? %s : ", temp_id.c_str(), temp_id.c_str());
+ f << stringf(") || %s == 0 ? $signed(%s) : ", temp_id.c_str(), temp_id.c_str());
dump_cell_expr_port(f, cell, "B", true);
f << stringf(" + $signed(%s);\n", temp_id.c_str());
return true;