| Commit message (Expand) | Author | Age | Files | Lines |
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| | * | | | | | | | abc9_ops: suppress -prep_box warning for abc9_flop | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
| | * | | | | | | | xilinx: Update RAMB* specify entries | Eddie Hung | 2020-02-27 | 1 | -11/+42 |
| | * | | | | | | | ice40: add delays to SB_CARRY | Eddie Hung | 2020-02-27 | 1 | -0/+30 |
| | * | | | | | | | xilinx: add delays to INV | Eddie Hung | 2020-02-27 | 1 | -0/+3 |
| | * | | | | | | | Make TimingInfo::TimingInfo(SigBit) constructor explicit | Eddie Hung | 2020-02-27 | 3 | -8/+9 |
| | * | | | | | | | TimingInfo: index by (port_name,offset) | Eddie Hung | 2020-02-27 | 2 | -12/+23 |
| | * | | | | | | | Fix spacing | Eddie Hung | 2020-02-27 | 2 | -68/+68 |
| | * | | | | | | | More +/ice40/cells_sim.v fixes | Eddie Hung | 2020-02-27 | 1 | -27/+27 |
| | * | | | | | | | Cleanup tests | Eddie Hung | 2020-02-27 | 2 | -1/+1 |
| | * | | | | | | | Update bug1630.ys to use -lut 4 instead of lut file | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
| | * | | | | | | | Make +/xilinx/cells_sim.v legal | Eddie Hung | 2020-02-27 | 1 | -76/+78 |
| | * | | | | | | | abc9_ops: still emit delay table even box has no timing | Eddie Hung | 2020-02-27 | 1 | -3/+1 |
| | * | | | | | | | write_xaiger: add comment about arrival times of flop outputs | Eddie Hung | 2020-02-27 | 1 | -0/+1 |
| | * | | | | | | | abc9_ops: demote lack of box timing info to warning | Eddie Hung | 2020-02-27 | 1 | -2/+4 |
| | * | | | | | | | Get rid of (* abc9_{arrival,required} *) entirely | Eddie Hung | 2020-02-27 | 6 | -651/+530 |
| | * | | | | | | | abc9_ops: use TimingInfo for -prep_{lut,box} too | Eddie Hung | 2020-02-27 | 2 | -25/+22 |
| | * | | | | | | | abc9_ops: use TimingInfo for -prep_{lut,box} too | Eddie Hung | 2020-02-27 | 3 | -97/+65 |
| | * | | | | | | | abc9_ops: add and use new TimingInfo struct | Eddie Hung | 2020-02-27 | 2 | -70/+214 |
| | * | | | | | | | Fix tests/arch/xilinx/fsm.ys to count flops only | Eddie Hung | 2020-02-27 | 1 | -9/+3 |
| | * | | | | | | | Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy | Eddie Hung | 2020-02-27 | 1 | -14/+12 |
| | * | | | | | | | ice40: fix specify for inverted clocks | Eddie Hung | 2020-02-27 | 1 | -27/+27 |
| | * | | | | | | | Fix tests by gating some specify constructs from iverilog | Eddie Hung | 2020-02-27 | 1 | -0/+16 |
| | * | | | | | | | Update simple_abc9 tests | Eddie Hung | 2020-02-27 | 3 | -5/+8 |
| | * | | | | | | | abc9_ops: ignore (* abc9_flop *) if not '-dff' | Eddie Hung | 2020-02-27 | 4 | -104/+114 |
| | * | | | | | | | ice40: specify fixes | Eddie Hung | 2020-02-27 | 3 | -66/+66 |
| | * | | | | | | | abc9_ops: sort LUT delays to be ascending | Eddie Hung | 2020-02-27 | 1 | -1/+4 |
| | * | | | | | | | ice40: move over to specify blocks for -abc9 | Eddie Hung | 2020-02-27 | 10 | -164/+1344 |
| | * | | | | | | | synth_ecp5: use +/abc9_model.v | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
| | * | | | | | | | Update xilinx for ABC9 | Eddie Hung | 2020-02-27 | 3 | -20/+16 |
| | * | | | | | | | Create +/abc9_model.v for $__ABC9_{DELAY,FF_} | Eddie Hung | 2020-02-27 | 2 | -0/+11 |
| | * | | | | | | | abc9_ops: output LUT area | Eddie Hung | 2020-02-27 | 1 | -6/+6 |
| | * | | | | | | | ecp5: remove small LUT entries | Eddie Hung | 2020-02-27 | 1 | -24/+6 |
| | * | | | | | | | abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTs | Eddie Hung | 2020-02-27 | 1 | -18/+33 |
| | * | | | | | | | Fix commented out specify statement | Eddie Hung | 2020-02-27 | 1 | -6/+6 |
| | * | | | | | | | xilinx: improve specify functionality | Eddie Hung | 2020-02-27 | 8 | -466/+547 |
| | * | | | | | | | ecp5: deprecate abc9_{arrival,required} and *.{lut,box} | Eddie Hung | 2020-02-27 | 7 | -86/+120 |
| | * | | | | | | | xilinx: use specify blocks in place of abc9_{arrival,required} | Eddie Hung | 2020-02-27 | 3 | -347/+670 |
| | * | | | | | | | Auto-generate .box/.lut files from specify blocks | Eddie Hung | 2020-02-27 | 8 | -466/+268 |
| | * | | | | | | | abc9_ops: assert on $specify2 properties | Eddie Hung | 2020-02-27 | 1 | -0/+3 |
| | * | | | | | | | abc9_ops: -prep_box, to be called once | Eddie Hung | 2020-02-27 | 3 | -51/+50 |
| | * | | | | | | | abc9_ops: -prep_lut and -write_lut to auto-generate LUT library | Eddie Hung | 2020-02-27 | 4 | -10/+200 |
| * | | | | | | | | Merge pull request #1729 from rqou/coolrunner2 | N. Engelhardt | 2020-03-02 | 3 | -109/+443 |
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| | * | | | | | | | | coolrunner2: Attempt to give wires/cells more meaningful names | R. Ou | 2020-03-02 | 2 | -23/+66 |
| | * | | | | | | | | coolrunner2: Fix invalid multiple fanouts of XOR/OR gates | R. Ou | 2020-03-02 | 1 | -0/+96 |
| | * | | | | | | | | coolrunner2: Fix packed register+input buffer insertion | R. Ou | 2020-03-02 | 1 | -2/+84 |
| | * | | | | | | | | coolrunner2: Insert many more required feedthrough cells | R. Ou | 2020-03-01 | 3 | -102/+215 |
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| * | | | | | | | | Merge pull request #1727 from YosysHQ/eddie/fix_write_smt2 | Eddie Hung | 2020-02-29 | 1 | -11/+11 |
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| | * | | | | | | | | ystests: fix write_smt2_write_smt2_cyclic_dependency_fail | Eddie Hung | 2020-02-28 | 1 | -11/+11 |
| * | | | | | | | | | Merge pull request #1726 from YosysHQ/eddie/fix1710 | Eddie Hung | 2020-02-28 | 2 | -9/+52 |
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| | * | | | | | | | | ast: fixes #1710; do not generate RTLIL for unreachable ternary | Eddie Hung | 2020-02-27 | 2 | -9/+52 |
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