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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 10:30:29 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 7c92b6852f3bcc962e72bb787ac51e3f4324a4fb (patch) | |
| tree | bc2010addc0bc4ef2f4f7be735a56505de1fbf88 | |
| parent | fb60d82971a9de5312467c4c192148ab546504dc (diff) | |
| download | yosys-7c92b6852f3bcc962e72bb787ac51e3f4324a4fb.tar.gz yosys-7c92b6852f3bcc962e72bb787ac51e3f4324a4fb.tar.bz2 yosys-7c92b6852f3bcc962e72bb787ac51e3f4324a4fb.zip | |
abc9_ops: sort LUT delays to be ascending
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 61a3880b7..e1ab70f11 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -617,7 +617,8 @@ void prep_lut(RTLIL::Design *design, int maxlut) } if (maxlut && GetSize(specify) > maxlut) continue; - // ABC requires ascending LUT input delays + // ABC requires non-decreasing LUT input delays + std::sort(specify.begin(), specify.end()); table.emplace_back(GetSize(specify), module->name, it->second.as_int(), std::move(specify)); } // ABC requires ascending size @@ -777,6 +778,8 @@ void prep_box(RTLIL::Design *design) log_assert(GetSize(src) == GetSize(dst)); for (auto i = 0; i < GetSize(src); i++) { auto r = table.insert(std::make_pair(src[i],dst[i])); + if (!r.second) + log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(src[i]), log_signal(dst[i])); log_assert(r.second); r.first->second = std::to_string(max); } |